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ZL50118/19/20 32, 64 and 128 Channel CESoP Processors
Data Sheet Features
General * * * * * Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchronization recovery across a packet network On chip dual reference Stratum 3 DPLL Grooming capability for Nx64 Kbps trunking Fully compatible with Zarlink's ZL50110, ZL50111 and ZL50114 CESoP processors
September 2004
Ordering Information ZL50118GAG ZL50119GAG ZL50120GAG 324 Ball PBGA 324 Ball PBGA 324 Ball PBGA
-40C to +85C Customer Side TDM Interfaces * * * * Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports H.110, H-MVIP, ST-BUS backplane Up to 128 bi-directional 64 Kbps channels Direct connection to LIUs, framers, backplanes
Circuit Emulation Services * * * * * Complies with ITU-T recommendation Y.1413 Complies with IETF PWE3 draft standards CESoPSN and SAToP Complies with CES draft IAs from MEF and MFA Structured, synchronous CES Unstructured, asynchronous CES with integral per-stream clock recovery
Customer Side or Provider Side Packet Interfaces * 100 Mbps MII Fast Ethernet
Provider Side Packet Interfaces * 100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet
4 T1/E1, 1 J2/T3/E3 or 1 STS-1 ports H.110, H-MVIP, ST-BUS backplanes
TDM Interface
(LIU, Framer, Backplane)
Multi-Protocol Packet Processing Engine
PW, RTP, UDP, IPv4, IPv6, MPLS, ECID, VLAN, User Defined, Others
Dual Packet Interface MAC
(MII, GMII, TBI)
Per Port DCO for Clock Recovery
100 Mbps MII Fast Ethernet
On Chip Packet Memory
(Jitter Buffer Compensation for 128 ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Host Processor Interface
32-bit Motorola compatible DMA for signaling packets
Backplane Clocks
JTAG
Figure 1 - ZL50118/19/20 High Level Overview
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Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet
ZL50118/19/20
System Interfaces * * Flexible 32 bit Motorola host interface
Data Sheet
On-chip packet memory with jitter buffer compensation for over 128 ms of packet delay variation
Packet Processing Functions * * * * * * Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF CESoPSN, IETF SAToP and user programmable Packet re-sequencing to allow lost packet detection and re-ordering Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues Programmable classification of incoming packets at layers 2 through 5 Wire speed processing of all packets regardless of classification providing low latency Supports up to 128 separate CES connections across the Packet Switched Network
Applications
* Circuit Emulation Services over Packet Networks * * * * * * * * Leased Line support over packet networks TDM over Cable TDM over WiFi (802.11x) TDM over WiMAX (802.16) Fibre To The Premises G/E-PON Layer 2 VPN services
Customer-premise and Provider Edge Routers and Switches Ethernet and IP based IADs
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Zarlink Semiconductor Inc.
ZL50118/19/20 Table of Contents
Data Sheet
1.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.1 TDM stream connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.2 TDM Signals common to ZL50118/19/20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.1 Administration, Control and Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7 Miscellaneous Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.9 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.10 No Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.11 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.0 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 Leased Line Provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 Remote Concentrator Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3 FTTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4 Wireless - WiFi or WiMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 Digital Loop Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6 Integrated Access Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1 TDM Interface Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.2 Structured TDM Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.3 TDM Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3.3.1 Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3.3.2 Asynchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4 Payload Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.1.1 Payload Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.6 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.7 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.8 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.9 Ethernet Traffic Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 Host Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4 Loss of Service (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5 Power Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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Zarlink Semiconductor Inc.
ZL50118/19/20 Table of Contents
Data Sheet
6.6 JTAG Interface and Board Level Test Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.7 External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.8 Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.9 Test Modes Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.9.1.1 System Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.9.1.2 System Tri-State Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.9.2 Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.9.3 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.9.4 System Tri-state Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.0 DPLL Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1.1 Locking Mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1.4 Powerdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.2 Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.3 Locking Mode Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.4 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.5 Locking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.6 Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.7 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.7.1 Acceptance of Input Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.7.2 Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.7.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.7.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.0 Memory Map and Register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.0 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.0 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1 TDM Interface Timing - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.1 ST-BUS Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.2 ST-BUS Master Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.2 TDM Interface Timing - H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3 TDM Interface Timing - H-MVIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4 TDM LIU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.5 PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.6 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.6.3 GMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.6.5 TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.7 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.8 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.9 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.1 High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.1.1 GMAC Interface - Special Considerations During Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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ZL50118/19/20 Table of Contents
Data Sheet
12.1.2 TDM Interface - Special Considerations During Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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ZL50118/19/20 List of Figures
Data Sheet
Figure 1 - ZL50118/19/20 High Level Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1 - ZL50118 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2 - ZL50119 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3 - ZL50120 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 - Leased Line Services Over a Circuit Emulation Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 5 - Remote Concentrator Unit using CESoP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 6 - EPON using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 7 - Wi-Fi and WiMAX using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 8 - Digital Loop Carrier using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 9 - Integrated Access Device Using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 10 - ZL50118/19/20 Family Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 11 - ZL50118/19/20 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 12 - Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 13 - ZL50118/19/20 Packet Format - Structured Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 14 - Channel Order for Packet Formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 15 - ZL50118/19/20 Packet Format - Unstructured Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 16 - Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 17 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 18 - Powering Up the ZL50118/19/20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 19 - Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 20 - Jitter Transfer Function - Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 21 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 22 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 23 - TDM Bus Master Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 24 - TDM Bus Master Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 25 - H.110 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 26 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 27 - TDM-LIU Structured Transmission/Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 28 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 29 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 30 - GMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 31 - GMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 32 - TBI Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 33 - TBI Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 34 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 35 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 36 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 37 - CPU Write - MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 38 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 39 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 40 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 41 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 42 - ZL50118/19/20 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 43 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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ZL50118/19/20 List of Tables
Data Sheet
Table 1 - Capacity of Devices in the ZL50118/19/20 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2 - ZL50118/19/20 Ball Signal Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3 - TDM Interface Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4 - TDM Interface Common Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5 - PAC Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7 - MII Management Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8 - MII Port 0 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9 - MII Port 1 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 10 - CPU Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 11 - System Function Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 12 - Administration/Control Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 13 - JTAG Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 14 - Miscellaneous Inputs Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 15 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 16 - Internal Connections Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 17 - Miscellaneous Inputs Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 18 - Device ID Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 19 - Standard Device Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 20 - TDM Services Offered by the ZL50118/19/20 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 21 - Some of the TDM Port Formats Accepted by the ZL50118/19/20 Family . . . . . . . . . . . . . . . . . . . . . . . 47 Table 22 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 23 - Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 24 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 25 - TDM ST-BUS Master Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 26 - TDM H.110 Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 27 - TDM H-MVIP Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 28 - TDM - LIU Structured Transmission/Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 29 - PAC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 30 - MII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 31 - MII Receive Timing - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 32 - GMII Transmit Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 33 - GMII Receive Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 34 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 35 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 36 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 37 - System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 38 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7
Zarlink Semiconductor Inc.
ZL50118/19/20
Description
Data Sheet
The ZL50118/19/20 family of CESoP processors are highly functional TDM to Packet bridging devices. The ZL50118/19/20 provides both structured and unstructured circuit emulation services (CES) for T1 and E1 streams across a packet network based on MPLS, IP or Ethernet. The ZL50120 also supports unstructured J2, T3, E3 and STS-1. The circuit emulation features in the ZL50118/19/20 family comply with the ITU Recommendation Y.1413, as well as the emerging CES standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay Alliance (MFA). The ZL50118/19/20 also complies with the standards currently being developed within the IETF's PWE3 working group, listed below. * * Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) draft-ietf-pwe3-cesopsn
The ZL50118/19/20 provides a customer side 100 Mbps MII port to aggregate data traffic with voice traffic to the provider side 1000 Mbps GMII/TBI port, thereby eliminating the need for an external Ethernet switch. The ZL50118/19/20 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. An externally supplied clock may also be used to drive the TDM interface of the ZL50118/19/20. The ZL50118/19/20 incur very low latency for the data flow, thereby increasing QoS when carrying voice services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation. The ZL50118/19/20 are cost effective devices aimed at the low density applications such as customer premise routers, IADs, ePON termination and Broadband DLCs. For network systems, the ZL50118/19/20 is fully compatible and interoperable with the ZL50110/11/14 family. The ZL50118/19/20 is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting them out the packet interfaces using a variety of protocols. The ZL50118/19/20 supports a range of different packet switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The devices also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. This can be used to help minimize latency variation in the TDM data. Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface. Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to maintain timing integrity. The ZL50118/19/20 includes on-chip memory sufficient for all applications, thereby reducing system costs, board area, power, and design complexity. A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that will run on a Windows PC.
8
Zarlink Semiconductor Inc.
ZL50118/19/20
Device Line Up
There are three products within the ZL50118/19/20 family, with capacities as shown in Table 1. Product Number ZL50118 Provider Side Packet Interface 100 Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII or 1000 Mbps GMII/TBI
Data Sheet
TDM Interface 1 T1 or 1 E1 stream or 1 MVIP/ST-BUS stream at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps 2 T1 or 2 E1 streams or 2 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps 4 T1 or 4 E1 streams or 1 J2, 1 T3, 1 E3 or 1 STS-1 stream or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
Customer Side Packet Interface 100 Mbps MII
ZL50119
100 Mbps MII
ZL50120
100 Mbps MII
Table 1 - Capacity of Devices in the ZL50118/19/20 Family
1.0
Physical Specification
The ZL50118/19/20 will be packaged in a PBGA device. Features: * * * * * * Body Size: Ball Count: Ball Pitch: Ball Matrix: Ball Diameter: Total Package Thickness: 23 mm x 23 mm (typ) 324 1.00 mm (typ) 22 x 22 0.60 mm (typ) 2.03 mm (typ)
9
Zarlink Semiconductor Inc.
ZL50118/19/20
ZL50118 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 A B C D E F G H J K L M N P R T U V W Y AA AB
VDD_IO
Data Sheet
2
3
4
5
6
7
8
9
10
11
12
13
GND
14
CPU_DATA[ 23]
15
GND
16
17
18
19
20
21
22
M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[ LK [4] 28] 24]
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1
M1_TXD[2]
VDD_IO
GND
M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER
GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ E_LED 27] 22] 20] 13]
GND
VDD_IO
CPU_TA
M1_TXD[3]
GND
VDD_IO M1_RXCLK M1_COL
M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0]
VDD_IO
VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO 31] P_LED 29] 26]
GND
CPU_DRE Q1
M1_RXD[1] M1_RXD[0] M1_RXD[2]
VDD_IO
M1_RXDV M0_RXER
VDD_IO
M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR E K E E
VDD_IO
M0_ACTIV VDD_COR E_LED E
VDD_IO CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6]
M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER T_LED
CPU_DATA[CPU_DATA[ CPU_DATA[ CPU_DATA[ 30] 21] 15] 14]
NC
M1_CRS DEVICE_ID VDD_COR [1] E
VDD_COR CPU_DATA[ CPU_DATA[ CPU_DATA[ E 18] 17] 16]
M_MDIO DEVICE_ID M0_LINKU [0] P_LED
VDD_IO
VDD_IO
CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0]
M_MDC
GND
NC
VDD_COR E
CPU_DATA[CPU_DATA[ CPU_DATA[ 10] 1] 4]
IC
NC
NC
NC
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[ CPU_DATA[ CPU_IREQ E 5] 3] 0
NC
NC
NC
VDD_IO
GND
GND
GND
GND
GND
GND
GND
CPU_DATA[ 2]
IC
CPU_DRE Q0
GND
AUX_CLKO AUX_CLKI VDD_COR E
GND
GND
GND
GND
GND
GND
CPU_CLK
GND
CPU_SDAC IC_VDD_IO K2
NC
NC
NC
VDD_IO
GND
GND
GND
GND
GND
GND
GND
CPU_TS_A CPU_WE LE
CPU_OE
NC
NC
NC
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_IO
CPU_ADD R[22]
CPU_CS CPU_ADDR [19]
NC
GND
VDD_IO
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21]
NC
NC
TDM_CLKI[ 0]
NC
GND
CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20]
NC
NC
TDM_FRMI _REF
VDD_IO
VDD_IO
VDD_IO CPU_ADDR CPU_ADDR [14] [16]
TDM_STI[0] VDD_IO
GND
TDM_CLKi S
VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12]
TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P
DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9]
IC
TDM_CLKI TDM_FRM _REF O_REF
VDD_IO
VDD_IO
VDD_COR E
VDD_IO
VDD_IO
VDD_COR PLL_SEC E
IC_GND
GND
SYSTEM_C VDD_COR LK E
GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO [2]
JTAG_TDO CPU_ADDR CPU_ADDR [4] [8]
IC
GND
VDD_IO
IC
IC
VDD_COR E
IC
IC
PLL_PRI
IC
IC_GND
IC
GND
GND
GPIO[8]
GPIO[14] TEST_MOD JTAG_TRS E[1] T
IC_GND
VDD_IO
GND
CPU_ADDR [7]
IC
VDD_IO
GND
VDD_IO
VDD_IO
IC
GND
A1VDD_PL L1
IC
IC
SYSTEM_D SYSTEM_R GPIO[1] EBUG ST
GPIO[2]
GPIO[7]
GPIO[12] TEST_MOD JTAG_TDI E[0]
IC_GND
GND
VDD_IO CPU_ADDR [6]
VDD_IO
IC
IC
IC
GND
IC
IC
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13] TEST_MOD IC_GND E[2]
CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5]
Figure 1 - ZL50118 Package View and Ball Positions
10
Zarlink Semiconductor Inc.
ZL50118/19/20
ZL50119 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 A B C D E F G H J K L M N P R T U V W Y AA AB
VDD_IO
Data Sheet
2
3
4
5
6
7
8
9
10
11
12
13
GND
14
CPU_DATA[ 23]
15
GND
16
17
18
19
20
21
22
M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[ LK [4] 28] 24]
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1
M1_TXD[2]
VDD_IO
GND
M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER
GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ E_LED 27] 22] 20] 13]
GND
VDD_IO
CPU_TA
M1_TXD[3]
GND
VDD_IO M1_RXCLK M1_COL
M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0]
VDD_IO
VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO 31] P_LED 29] 26]
GND
CPU_DRE Q1
M1_RXD[1] M1_RXD[0] M1_RXD[2]
VDD_IO
M1_RXDV M0_RXER
VDD_IO
M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR E K E E
VDD_IO
M0_ACTIV VDD_COR E_LED E
VDD_IO CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6]
M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER T_LED
CPU_DATA[CPU_DATA[ CPU_DATA[ CPU_DATA[ 30] 21] 15] 14]
NC
M1_CRS DEVICE_ID VDD_COR [1] E
VDD_COR CPU_DATA[ CPU_DATA[ CPU_DATA[ E 18] 17] 16]
M_MDIO DEVICE_ID M0_LINKU [0] P_LED
VDD_IO
VDD_IO
CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0]
M_MDC
GND
NC
VDD_COR E
CPU_DATA[CPU_DATA[ CPU_DATA[ 10] 1] 4]
IC
NC
NC
NC
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[ CPU_DATA[ CPU_IREQ E 5] 3] 0
NC
NC
NC
VDD_IO
GND
GND
GND
GND
GND
GND
GND
CPU_DATA[ 2]
IC
CPU_DRE Q0
GND
AUX_CLKO AUX_CLKI VDD_COR E
GND
GND
GND
GND
GND
GND
CPU_CLK
GND
CPU_SDAC IC_VDD_IO K2
NC
NC
NC
VDD_IO
GND
GND
GND
GND
GND
GND
GND
CPU_TS_A CPU_WE LE
CPU_OE
NC
NC
NC
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_IO
CPU_ADD R[22]
CPU_CS CPU_ADDR [19]
NC
GND
VDD_IO
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21]
NC
TDM_STI[1] TDM_CLKI[ TDM_STO[ 0] 1]
GND
CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20]
TDM_CLKI[ TDM_CLKO TDM_FRMI 1] [1] _REF
VDD_IO
VDD_IO
VDD_IO CPU_ADDR CPU_ADDR [14] [16]
TDM_STI[0] VDD_IO
GND
TDM_CLKi S
VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12]
TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P
DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9]
IC
TDM_CLKI TDM_FRM _REF O_REF
VDD_IO
VDD_IO
VDD_COR E
VDD_IO
VDD_IO
VDD_COR PLL_SEC E
IC_GND
GND
SYSTEM_C VDD_COR LK E
GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO [2]
JTAG_TDO CPU_ADDR CPU_ADDR [4] [8]
IC
GND
VDD_IO
IC
IC
VDD_COR E
IC
IC
PLL_PRI
IC
IC_GND
IC
GND
GND
GPIO[8]
GPIO[14] TEST_MOD JTAG_TRS E[1] T
IC_GND
VDD_IO
GND
CPU_ADDR [7]
IC
VDD_IO
GND
VDD_IO
VDD_IO
IC
GND
A1VDD_PL L1
IC
IC
SYSTEM_D SYSTEM_R GPIO[1] EBUG ST
GPIO[2]
GPIO[7]
GPIO[12] TEST_MOD JTAG_TDI E[0]
IC_GND
GND
VDD_IO CPU_ADDR [6]
VDD_IO
IC
IC
IC
GND
IC
IC
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13] TEST_MOD IC_GND E[2]
CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5]
Figure 2 - ZL50119 Package View and Ball Positions
11
Zarlink Semiconductor Inc.
ZL50118/19/20
ZL50120 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 A B C D E F G H J K L M N P R T U V W Y AA AB
VDD_IO
Data Sheet
2
3
4
5
6
7
8
9
10
11
12
13
GND
14
CPU_DATA[ 23]
15
GND
16
17
18
19
20
21
22
M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[ LK [4] 28] 24]
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1
M1_TXD[2]
VDD_IO
GND
M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER
GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ E_LED 27] 22] 20] 13]
GND
VDD_IO
CPU_TA
M1_TXD[3]
GND
VDD_IO M1_RXCLK M1_COL
M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0]
VDD_IO
VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO 31] P_LED 29] 26]
GND
CPU_DRE Q1
M1_RXD[1] M1_RXD[0] M1_RXD[2]
VDD_IO
M1_RXDV M0_RXER
VDD_IO
M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR E K E E
VDD_IO
M0_ACTIV VDD_COR E_LED E
VDD_IO CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6]
M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER T_LED
CPU_DATA[CPU_DATA[ CPU_DATA[ CPU_DATA[ 30] 21] 15] 14]
NC
M1_CRS DEVICE_ID VDD_COR [1] E
VDD_COR CPU_DATA[ CPU_DATA[ CPU_DATA[ E 18] 17] 16]
M_MDIO DEVICE_ID M0_LINKU [0] P_LED
VDD_IO
VDD_IO
CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0]
M_MDC
GND
NC
VDD_COR E
CPU_DATA[CPU_DATA[ CPU_DATA[ 10] 1] 4]
IC
NC
NC
NC
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[ CPU_DATA[ CPU_IREQ E 5] 3] 0
NC
NC
NC
VDD_IO
GND
GND
GND
GND
GND
GND
GND
CPU_DATA[ 2]
IC
CPU_DRE Q0
GND
AUX_CLKO AUX_CLKI VDD_COR E
GND
GND
GND
GND
GND
GND
CPU_CLK
GND
CPU_SDAC IC_VDD_IO K2
TDM_CLKI[ TDM_STO[ TDM_STI[3] VDD_IO 3] 3]
GND
GND
GND
GND
GND
GND
GND
CPU_TS_A CPU_WE LE
CPU_OE
TDM_STO[ TDM_CLKO TDM_STI[2] VDD_COR 2] [3] E
GND
GND
GND
GND
GND
GND
VDD_IO
CPU_ADD R[22]
CPU_CS CPU_ADDR [19]
TDM_CLKI[ 2]
GND
VDD_IO
VDD_COR E
GND
GND
GND
GND
GND
GND
VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21]
TDM_CLKO TDM_STI[1] TDM_CLKI[ TDM_STO[ [2] 0] 1]
GND
CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20]
TDM_CLKI[ TDM_CLKO TDM_FRMI 1] [1] _REF
VDD_IO
VDD_IO
VDD_IO CPU_ADDR CPU_ADDR [14] [16]
TDM_STI[0] VDD_IO
GND
TDM_CLKi S
VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12]
TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P
DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9]
IC
TDM_CLKI TDM_FRM _REF O_REF
VDD_IO
VDD_IO
VDD_COR E
VDD_IO
VDD_IO
VDD_COR PLL_SEC E
IC_GND
GND
SYSTEM_C VDD_COR LK E
GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO [2]
JTAG_TDO CPU_ADDR CPU_ADDR [4] [8]
IC
GND
VDD_IO
IC
IC
VDD_COR E
IC
IC
PLL_PRI
IC
IC_GND
IC
GND
GND
GPIO[8]
GPIO[14] TEST_MOD JTAG_TRS E[1] T
IC_GND
VDD_IO
GND
CPU_ADDR [7]
IC
VDD_IO
GND
VDD_IO
VDD_IO
IC
GND
A1VDD_PL L1
IC
IC
SYSTEM_D SYSTEM_R GPIO[1] EBUG ST
GPIO[2]
GPIO[7]
GPIO[12] TEST_MOD JTAG_TDI E[0]
IC_GND
GND
VDD_IO CPU_ADDR [6]
VDD_IO
IC
IC
IC
GND
IC
IC
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13] TEST_MOD IC_GND E[2]
CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5]
Figure 3 - ZL50120 Package View and Ball Positions
12
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A2 A3 A4 A5 A6 A7 A8 A9 B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 ZL50118 Signal Name VDD_IO DEVICE_ID[4] CPU_DATA[28] CPU_DATA[24] GND CPU_DATA[23] GND CPU_DATA[19] CPU_DATA[12] CPU_DATA[9] CPU_DATA[8] CPU_DATA[7] CPU_SDACK1 VDD_IO M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_CLK M0_TXEN M1_TXD[2] M0_TXER GND M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIVE_LED CPU_DATA[27] CPU_DATA[22] CPU_DATA[20] CPU_DATA[13] ZL50119 Signal Name VDD_IO DEVICE_ID[4] CPU_DATA[28] CPU_DATA[24] GND CPU_DATA[23] GND CPU_DATA[19] CPU_DATA[12] CPU_DATA[9] CPU_DATA[8] CPU_DATA[7] CPU_SDACK1 VDD_IO M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_CLK M0_TXEN M1_TXD[2] M0_TXER GND M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIVE_LED CPU_DATA[27] CPU_DATA[22] CPU_DATA[20] CPU_DATA[13] ZL50120 Signal Name VDD_IO DEVICE_ID[4] CPU_DATA[28] CPU_DATA[24] GND CPU_DATA[23] GND CPU_DATA[19] CPU_DATA[12] CPU_DATA[9] CPU_DATA[8] CPU_DATA[7] CPU_SDACK1 VDD_IO M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_CLK M0_TXEN M1_TXD[2] M0_TXER GND M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIVE_LED CPU_DATA[27] CPU_DATA[22] CPU_DATA[20] CPU_DATA[13] All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment
13
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # B20 B21 B22 B2 B3 B4 B5 B6 B7 B8 B9 C1 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C2 C3 C4 C5 C6 C7 C8 C9 ZL50118 Signal Name GND VDD_IO CPU_TA VDD_IO GND M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M1_TXD[3] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO VDD_IO CPU_DATA[31] M1_LINKUP_LED CPU_DATA[29] CPU_DATA[26] VDD_IO GND CPU_DREQ1 GND VDD_IO M1_RXCLK M1_COL M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] ZL50119 Signal Name GND VDD_IO CPU_TA VDD_IO GND M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M1_TXD[3] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO VDD_IO CPU_DATA[31] M1_LINKUP_LED CPU_DATA[29] CPU_DATA[26] VDD_IO GND CPU_DREQ1 GND VDD_IO M1_RXCLK M1_COL M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] ZL50120 Signal Name GND VDD_IO CPU_TA VDD_IO GND M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M1_TXD[3] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO VDD_IO CPU_DATA[31] M1_LINKUP_LED CPU_DATA[29] CPU_DATA[26] VDD_IO GND CPU_DREQ1 GND VDD_IO M1_RXCLK M1_COL M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
14
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D2 D3 D4 D5 D6 D7 D8 D9 E1 E19 E20 E21 E22 E2 E3 E4 F1 F19 F20 ZL50118 Signal Name M1_RXD[1] M0_RXD[2] M0_REFCLK M0_TXD[6] M0_TXD[1] VDD_CORE VDD_CORE VDD_IO M0_ACTIVE_LED VDD_CORE VDD_IO CPU_DATA[25] CPU_ADDR[23] CPU_DATA[6] M1_RXD[0] M1_RXD[2] VDD_IO M1_RXDV M0_RXER VDD_IO M0_RXD[5] VDD_CORE M1_RXD[3] CPU_DATA[30] CPU_DATA[21] CPU_DATA[15] CPU_DATA[14] M0_GIGABIT_LED M1_TXCLK M1_RXER NC VDD_CORE CPU_DATA[18] ZL50119 Signal Name M1_RXD[1] M0_RXD[2] M0_REFCLK M0_TXD[6] M0_TXD[1] VDD_CORE VDD_CORE VDD_IO M0_ACTIVE_LED VDD_CORE VDD_IO CPU_DATA[25] CPU_ADDR[23] CPU_DATA[6] M1_RXD[0] M1_RXD[2] VDD_IO M1_RXDV M0_RXER VDD_IO M0_RXD[5] VDD_CORE M1_RXD[3] CPU_DATA[30] CPU_DATA[21] CPU_DATA[15] CPU_DATA[14] M0_GIGABIT_LED M1_TXCLK M1_RXER NC VDD_CORE CPU_DATA[18] ZL50120 Signal Name M1_RXD[1] M0_RXD[2] M0_REFCLK M0_TXD[6] M0_TXD[1] VDD_CORE VDD_CORE VDD_IO M0_ACTIVE_LED VDD_CORE VDD_IO CPU_DATA[25] CPU_ADDR[23] CPU_DATA[6] M1_RXD[0] M1_RXD[2] VDD_IO M1_RXDV M0_RXER VDD_IO M0_RXD[5] VDD_CORE M1_RXD[3] CPU_DATA[30] CPU_DATA[21] CPU_DATA[15] CPU_DATA[14] M0_GIGABIT_LED M1_TXCLK M1_RXER NC VDD_CORE CPU_DATA[18] All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
15
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # F21 F22 F2 F3 F4 G1 G19 G20 G21 G22 G2 G3 G4 H1 H19 H20 H21 H22 H2 H3 H4 J1 J10 J11 J12 J13 J14 J19 J20 J21 J22 J2 J3 ZL50118 Signal Name CPU_DATA[17] CPU_DATA[16] M1_CRS DEVICE_ID[1] VDD_CORE M_MDIO VDD_IO CPU_IREQ1 CPU_DATA[11] CPU_DATA[0] DEVICE_ID[0] M0_LINKUP_LED VDD_IO M_MDC CPU_DATA[10] CPU_DATA[1] CPU_DATA[4] IC GND NC VDD_CORE NC GND GND GND GND GND VDD_CORE CPU_DATA[5] CPU_DATA[3] CPU_IREQ0 NC NC ZL50119 Signal Name CPU_DATA[17] CPU_DATA[16] M1_CRS DEVICE_ID[1] VDD_CORE M_MDIO VDD_IO CPU_IREQ1 CPU_DATA[11] CPU_DATA[0] DEVICE_ID[0] M0_LINKUP_LED VDD_IO M_MDC CPU_DATA[10] CPU_DATA[1] CPU_DATA[4] IC GND NC VDD_CORE NC GND GND GND GND GND VDD_CORE CPU_DATA[5] CPU_DATA[3] CPU_IREQ0 NC NC ZL50120 Signal Name CPU_DATA[17] CPU_DATA[16] M1_CRS DEVICE_ID[1] VDD_CORE M_MDIO VDD_IO CPU_IREQ1 CPU_DATA[11] CPU_DATA[0] DEVICE_ID[0] M0_LINKUP_LED VDD_IO M_MDC CPU_DATA[10] CPU_DATA[1] CPU_DATA[4] IC GND NC VDD_CORE NC GND GND GND GND GND VDD_CORE CPU_DATA[5] CPU_DATA[3] CPU_IREQ0 NC NC All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
16
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # J4 J9 K1 K10 K11 K12 K13 K14 K19 K20 K21 K22 K2 K3 K4 K9 L1 L10 L11 L12 L13 L14 L19 L20 L21 L22 L2 L3 L4 L9 M1 M10 M11 ZL50118 Signal Name VDD_CORE GND NC GND GND GND GND GND GND CPU_DATA[2] IC CPU_DREQ0 NC NC VDD_IO GND GND GND GND GND GND GND CPU_CLK GND CPU_SDACK2 IC_VDD_IO AUX_CLKO AUX_CLKI VDD_CORE GND NC GND GND ZL50119 Signal Name VDD_CORE GND NC GND GND GND GND GND GND CPU_DATA[2] IC CPU_DREQ0 NC NC VDD_IO GND GND GND GND GND GND GND CPU_CLK GND CPU_SDACK2 IC_VDD_IO AUX_CLKO AUX_CLKI VDD_CORE GND NC GND GND ZL50120 Signal Name VDD_CORE GND NC GND GND GND GND GND GND CPU_DATA[2] IC CPU_DREQ0 NC NC VDD_IO GND GND GND GND GND GND GND CPU_CLK GND CPU_SDACK2 IC_VDD_IO AUX_CLKO AUX_CLKI VDD_CORE GND TDM_CLKI[3] GND GND All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All ZL50120 All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
17
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # M12 M13 M14 M19 M20 M21 M22 M2 M3 M4 M9 N1 N10 N11 N12 N13 N14 N19 N20 N21 N22 N2 N3 N4 N9 P1 P10 P11 P12 P13 P14 P19 P20 ZL50118 Signal Name GND GND GND GND CPU_TS_ALE CPU_WE CPU_OE NC NC VDD_IO GND NC GND GND GND GND GND VDD_IO CPU_ADDR[22] CPU_CS CPU_ADDR[19] NC NC VDD_CORE GND NC GND GND GND GND GND VDD_CORE CPU_ADDR[17] ZL50119 Signal Name GND GND GND GND CPU_TS_ALE CPU_WE CPU_OE NC NC VDD_IO GND NC GND GND GND GND GND VDD_IO CPU_ADDR[22] CPU_CS CPU_ADDR[19] NC NC VDD_CORE GND NC GND GND GND GND GND VDD_CORE CPU_ADDR[17] ZL50120 Signal Name GND GND GND GND CPU_TS_ALE CPU_WE CPU_OE TDM_STO[3] TDM_STI[3] VDD_IO GND TDM_STO[2] GND GND GND GND GND VDD_IO CPU_ADDR[22] CPU_CS CPU_ADDR[19] TDM_CLKO[3] TDM_STI[2] VDD_CORE GND TDM_CLKI[2] GND GND GND GND GND VDD_CORE CPU_ADDR[17] All All All All All All All ZL50120 ZL50120 All All ZL50120 All All All All All All All All All ZL50120 ZL50120 All All ZL50120 All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
18
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # P21 P22 P2 P3 P4 P9 R1 R19 R20 R21 R22 R2 R3 R4 T1 T19 T20 T21 T22 T2 T3 T4 U1 U19 U20 U21 U22 U2 U3 U4 V1 V19 V20 ZL50118 Signal Name CPU_ADDR[18] CPU_ADDR[21] GND VDD_IO VDD_CORE GND NC GND CPU_ADDR[11] CPU_ADDR[13] CPU_ADDR[20] NC TDM_CLKI[0] NC NC VDD_IO VDD_IO CPU_ADDR[14] CPU_ADDR[16] NC TDM_FRMI_REF VDD_IO TDM_STI[0] VDD_CORE JTAG_TMS CPU_ADDR[15] CPU_ADDR[12] VDD_IO GND TDM_CLKiS TDM_STO[0] DEVICE_ID[3] JTAG_TCK ZL50119 Signal Name CPU_ADDR[18] CPU_ADDR[21] GND VDD_IO VDD_CORE GND NC GND CPU_ADDR[11] CPU_ADDR[13] CPU_ADDR[20] TDM_STI[1] TDM_CLKI[0] TDM_STO[1] TDM_CLKI[1] VDD_IO VDD_IO CPU_ADDR[14] CPU_ADDR[16] TDM_CLKO[1] TDM_FRMI_REF VDD_IO TDM_STI[0] VDD_CORE JTAG_TMS CPU_ADDR[15] CPU_ADDR[12] VDD_IO GND TDM_CLKiS TDM_STO[0] DEVICE_ID[3] JTAG_TCK ZL50120 Signal Name CPU_ADDR[18] CPU_ADDR[21] GND VDD_IO VDD_CORE GND TDM_CLKO[2] GND CPU_ADDR[11] CPU_ADDR[13] CPU_ADDR[20] TDM_STI[1] TDM_CLKI[0] TDM_STO[1] TDM_CLKI[1] VDD_IO VDD_IO CPU_ADDR[14] CPU_ADDR[16] TDM_CLKO[1] TDM_FRMI_REF VDD_IO TDM_STI[0] VDD_CORE JTAG_TMS CPU_ADDR[15] CPU_ADDR[12] VDD_IO GND TDM_CLKiS TDM_STO[0] DEVICE_ID[3] JTAG_TCK All All All All All All ZL50120 All All All All ZL50119/20 All ZL50119/20 ZL50119/20 All All All All ZL50119/20 All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
19
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # V21 V22 V2 V3 V4 W1 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W2 W3 W4 W5 W6 W7 W8 W9 Y1 Y10 Y11 Y12 Y13 Y14 ZL50118 Signal Name CPU_ADDR[10] CPU_ADDR[9] TDM_CLKO[0] TDM_CLKO_REF TDM_CLKiP IC PLL_SEC IC_GND GND SYSTEM_CLK VDD_CORE GPIO[9] VDD_IO GPIO[15] DEVICE_ID[2] VDD_IO JTAG_TDO CPU_ADDR[4] CPU_ADDR[8] TDM_CLKI_REF TDM_FRMO_REF VDD_IO VDD_IO VDD_CORE VDD_IO VDD_IO VDD_CORE IC IC IC_GND IC GND GND ZL50119 Signal Name CPU_ADDR[10] CPU_ADDR[9] TDM_CLKO[0] TDM_CLKO_REF TDM_CLKiP IC PLL_SEC IC_GND GND SYSTEM_CLK VDD_CORE GPIO[9] VDD_IO GPIO[15] DEVICE_ID[2] VDD_IO JTAG_TDO CPU_ADDR[4] CPU_ADDR[8] TDM_CLKI_REF TDM_FRMO_REF VDD_IO VDD_IO VDD_CORE VDD_IO VDD_IO VDD_CORE IC IC IC_GND IC GND GND ZL50120 Signal Name CPU_ADDR[10] CPU_ADDR[9] TDM_CLKO[0] TDM_CLKO_REF TDM_CLKiP IC PLL_SEC IC_GND GND SYSTEM_CLK VDD_CORE GPIO[9] VDD_IO GPIO[15] DEVICE_ID[2] VDD_IO JTAG_TDO CPU_ADDR[4] CPU_ADDR[8] TDM_CLKI_REF TDM_FRMO_REF VDD_IO VDD_IO VDD_CORE VDD_IO VDD_IO VDD_CORE IC IC IC_GND IC GND GND All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
20
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 AA1 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA2 AA3 AA4 ZL50118 Signal Name GPIO[8] GPIO[14] TEST_MODE[1] JTAG_TRST IC_GND VDD_IO GND CPU_ADDR[7] GND VDD_IO IC IC VDD_CORE IC IC PLL_PRI IC IC SYSTEM_DEBUG SYSTEM_RST GPIO[1] GPIO[2] GPIO[7] GPIO[12] TEST_MODE[0] JTAG_TDI IC_GND GND VDD_IO CPU_ADDR[6] VDD_IO GND VDD_IO ZL50119 Signal Name GPIO[8] GPIO[14] TEST_MODE[1] JTAG_TRST IC_GND VDD_IO GND CPU_ADDR[7] GND VDD_IO IC IC VDD_CORE IC IC PLL_PRI IC IC SYSTEM_DEBUG SYSTEM_RST GPIO[1] GPIO[2] GPIO[7] GPIO[12] TEST_MODE[0] JTAG_TDI IC_GND GND VDD_IO CPU_ADDR[6] VDD_IO GND VDD_IO ZL50120 Signal Name GPIO[8] GPIO[14] TEST_MODE[1] JTAG_TRST IC_GND VDD_IO GND CPU_ADDR[7] GND VDD_IO IC IC VDD_CORE IC IC PLL_PRI IC IC SYSTEM_DEBUG SYSTEM_RST GPIO[1] GPIO[2] GPIO[7] GPIO[12] TEST_MODE[0] JTAG_TDI IC_GND GND VDD_IO CPU_ADDR[6] VDD_IO GND VDD_IO All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
21
Zarlink Semiconductor Inc.
ZL50118/19/20
Ball # AA5 AA6 AA7 AA8 AA9 AB1 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 ZL50118 Signal Name VDD_IO IC GND A1VDD_PLL1 IC VDD_IO GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] GPIO[11] GPIO[13] TEST_MODE[2] IC_GND CPU_ADDR[2] CPU_ADDR[3] CPU_ADDR[5] VDD_IO IC IC IC GND IC IC IC GPIO[0] ZL50119 Signal Name VDD_IO IC GND A1VDD_PLL1 IC VDD_IO GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] GPIO[11] GPIO[13] TEST_MODE[2] IC_GND CPU_ADDR[2] CPU_ADDR[3] CPU_ADDR[5] VDD_IO IC IC IC GND IC IC IC GPIO[0] ZL50120 Signal Name VDD_IO IC GND A1VDD_PLL1 IC VDD_IO GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] GPIO[11] GPIO[13] TEST_MODE[2] IC_GND CPU_ADDR[2] CPU_ADDR[3] CPU_ADDR[5] VDD_IO IC IC IC GND IC IC IC GPIO[0] All All All All All All All All All All All All All All All All All All All All All All All All All All All Variant
Data Sheet
Table 2 - ZL50118/19/20 Ball Signal Assignment (continued)
NC - Not Connected - leave open circuit. IC - Internally Connected - leave open circuit. IC_GND - Internally Connected - tie to ground IC_VDD_IO - Internally Connected - tie to VDD_IO
22
Zarlink Semiconductor Inc.
ZL50118/19/20
2.0 External Interface Description
Data Sheet
The following key applies to all tables: I O D U T Input Output Internal 100 k pull-down resistor present Internal 100 k pull-up resistor present Tri-state Output
2.1
TDM Interface
All TDM Interface signals are 5 V tolerant. All TDM Interface outputs are high impedance while System Reset is LOW. All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used.
2.1.1
TDM stream connections
There are three interfaces possible among the ZL50118/19/20. The ZL50120 supports four TDM ports [3:0] at 2 Mbps, or one TDM port [0] at 8 Mbps or one unstructured TDM port [0] for J2/E3/T3/STS-1. The ZL50119 supports two TDM ports [1:0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 64 DS0). The ZL50118 supports one TDM port [0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 32 DS0) Signal TDM_STi[3:0] I/O ID [3] [2] [1] [0] M3 N3 R2 U1 Package Balls Description TDM port serial data input streams. For different standards these pins are given different identities: ST-BUS: TDM_STi[3:0] H.110: TDM_D[3:0] H-MVIP: TDM_HDS[3:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50120.
Table 3 - TDM Interface Stream Pin Definition
23
Zarlink Semiconductor Inc.
ZL50118/19/20
Signal TDM_STo[3:0] I/O OT [3] [2] [1] [0] M2 N1 R4 V1 Package Balls Description
Data Sheet
TDM port serial data output streams. For different standards these pins are given different identities: ST-BUS: TDM_STo[3:0] H.110: TDM_D[3:0] H-MVIP: TDM_HDS[3:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50120. TDM port clock inputs programmable as active high or low. Can accept frequencies of 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 6.312 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50120. TDM port clock outputs. Will generate 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50120.
TDM_CLKi[3:0]
ID
[3] [2] [1] [0]
M1 P1 T1 R3
TDM_CLKo[3:0]
OT
[3] [2] [1] [0]
N2 R1 T2 V2
Table 3 - TDM Interface Stream Pin Definition
Note: Speed modes: 2.048 Mbps - 32 channels per stream. 8.192 Mbps - 128 channels per stream. J2 - 98 channels per stream E3 - 537 channels per stream T3 - 699 channels per stream Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used.
24
Zarlink Semiconductor Inc.
ZL50118/19/20
2.1.2 TDM Signals common to ZL50118/19/20
Signal TDM_CLKi_REF TDM_CLKo_REF TDM_FRMi_REF I/O ID O ID W2 V3 T3 Package Balls Description
Data Sheet
TDM port reference clock input for backplane operation TDM port reference clock output for backplane operation TDM port reference frame input. For different standards this pin is given a different identity: ST-BUS: TDM_F0i H.110: TDM_FRAME H-MVIP: TDM_F0 Signal is normally active low, but can be active high depending on standard. Indicates the start of a TDM frame by pulsing every 125 s. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. TDM port reference frame output. For different standards this pin is given a different identity: ST-BUS: TDM_F0o H.110: TDM_FRAME H-MVIP: TDM_F0 Signal is normally active low, but can be active high depending on standard. Indicates the start of a TDM frame by pulsing every 125 s. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. Auxiliary clock input. Typically connected to AUX_CLKO. Auxiliary clock output. Typically connected to AUX_CLKI.
TDM_FRMo_REF
O
W3
AUX_CLKI AUX_CLKO
ID OT
L3 L2
Table 4 - TDM Interface Common Pin Definition
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Zarlink Semiconductor Inc.
ZL50118/19/20
2.2 PAC Interface
Data Sheet
All PAC Interface signals are 5 V tolerant. All PAC Interface outputs are high impedance while System Reset is LOW. Signal TDM_CLKiP I/O ID V4 Package Balls Description Primary reference clock input. Should be driven by external clock source to provide locking reference to internal / optional external DPLL in TDM master mode. Also provides PRS clock for RTP timestamps in synchronous modes. Acceptable frequency range: 8 kHz 34.368 MHz. Secondary reference clock input. Backup external reference for automatic switch-over in case of failure of TDM_CLKiP source. Primary reference output to optional external DPLL. Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz. Secondary reference output to optional external DPLL Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz.
TDM_CLKiS
ID
U4
PLL_PRI
OT
Y9
PLL_SEC
OT
W10
Table 5 - PAC Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50118/19/20
2.3 Packet Interfaces
Data Sheet
For the ZL50118/19/20 variants the packet interface is capable of either 2 MII interfaces, or 1 MII and 1 GMII interfaces, or 1 MII and 1 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an integrated 1000BASE-X PCS module. Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. Only Port 0 has the 1000 Mbps capability necessary for the GMII/TBI interface. Table 6 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 7 shows all the pins and their related package ball, but is based on the GMII/MII configuration. All Packet Interface signals are 5V tolerant, and all outputs are high impedance while System Reset is LOW. MII Mn_LINKUP_LED Mn_ACTIVE_LED Mn_RXCLK Mn_COL Mn_RXD[3:0] Mn_RXDV Mn_RXER Mn_CRS Mn_TXCLK Mn_TXD[3:0] Mn_TXEN Mn_TXER GMII Mn_LINKUP_LED Mn_ACTIVE_LED Mn_GIGABIT_LED Mn_REFCLK Mn_RXCLK Mn_COL Mn_RXD[7:0] Mn_RXDV Mn_RXER Mn_CRS Mn_TXD[7:0] Mn_TXEN Mn_TXER Mn_GTX_CLK TBI (PCS) Mn_LINKUP_LED Mn_ACTIVE_LED Mn_GIGABIT_LED Mn_REFCLK Mn_RBC0 Mn_RBC1 Mn_RXD[7:0] Mn_RXD[8] Mn_RXD[9] Mn_Signal_Detect Mn_TXD[7:0] Mn_TXD[8] Mn_TXD[9] Mn_GTX_CLK
Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI
Note: Mn can be either M0 or M1 for ZL50118/19/20 variants.
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Zarlink Semiconductor Inc.
ZL50118/19/20
Signal M_MDC I/O O H1 Package Balls Description
Data Sheet
MII management data clock. Common for all four MII ports. It has a minimum period of 400ns (maximum freq. 2.5 MHz), and is independent of the TXCLK and RXCLK. MII management data I/O. Common for all four MII ports at up to 2.5 MHz. It is bi-directional between the ZL50118/19/20 and the Ethernet station management entity. Data is passed synchronously with respect to M_MDC.
M_MDIO
ID/ OT
G1
Table 7 - MII Management Interface Package Ball Definition
MII Port 0 Signal M0_LINKUP_LED I/O O G3 Package Balls Description LED drive for MAC 0 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 0 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 0 to indicate operation at Gbps. Logic 0 output = LED on Logic 1 output = LED off GMII/TBI - Reference Clock input at 125 MHz. Can be used to lock receive circuitry (RX) to M0_GTXCLK rather than recovering the RXCLK (or RBC0 and RBC1). Useful, for example, in the absence of valid serial data. NOTE: In MII mode this pin must be driven with the same clock as M0_RXCLK. GMII/MII - M0_RXCLK. Accepts the following frequencies: 25.0 MHz MII 100 Mbps 125.0 MHz GMII 1 Gbps
M0_ACTIVE_LED
O
D17
M0_GIGABIT_LED
O
E2
M0_REFCLK
ID
D11
M0_RXCLK
IU
C10
Table 8 - MII Port 0 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50118/19/20
MII Port 0 Signal M0_RBC0 I/O IU B9 Package Balls Description
Data Sheet
TBI - M0_RBC0. Used as a clock when in TBI mode. Accepts 62.5 MHz and is 180C out of phase with M0_RBC1. Receive data is clocked at each rising edge of M0_RBC1 and M0_RBC0, resulting in 125 MHz sample rate. TBI - M0_RBC1 Used as a clock when in TBI mode. Accepts 62.5 MHz, and is 180 out of phase with M0_RBC0. Receive data is clocked at each rising edge of M0_RBC1 and M0_RBC0, resulting in 125 MHz sample rate. GMII/MII - M0_COL. Collision Detection. This signal is independent of M0_TXCLK and M0_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation. A4 A5 D8 A6 [3] [2] [1] [0] C8 D10 C9 B7 Receive Data. Only half the bus (bits [3:0]) are used in MII mode. Clocked on rising edge of M0_RXCLK (GMII/MII) or the rising edges of M0_RBC0 and M0_RBC1 (TBI). GMII/MII - M0_RXDV Receive Data Valid. Active high. This signal is clocked on the rising edge of M0_RXCLK. It is asserted when valid data is on the M0_RXD bus. TBI - M0_RXD[8] Receive Data. Clocked on the rising edges of M0_RBC0 and M0_RBC1. GMII/MII - M0_RXER Receive Error. Active high signal indicating an error has been detected. Normally valid when M0_RXDV is asserted. Can be used in conjunction with M0_RXD when M0_RXDV signal is de-asserted to indicate a False Carrier. TBI - M0_RXD[9] Receive Data. Clocked on the rising edges of M0_RBC0 and M0_RBC1.
M0_RBC1
IU
B8
M0_COL
ID
A7
M0_RXD[7:0]
IU
[7] [6] [5] [4] C7
M0_RXDV / M0_RXD[8]
ID
M0_RXER / M0_RXD[9]
ID
D6
Table 8 - MII Port 0 Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50118/19/20
MII Port 0 Signal M0_CRS / M0_Signal_Detect I/O ID B6 Package Balls Description
Data Sheet
GMII/MII - M0_CRS Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. TBI - M0_Signal Detect Similar function to M0_CRS. MII only - Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbps C11 D12 B12 C12 [3] [2] [1] [0] B13 B14 D13 C13 Transmit Data. Only half the bus (bits [3:0]) are used in MII mode. Clocked on rising edge of M0_TXCLK (MII) or the rising edge of M0_GTXCLK (GMII/TBI). GMII/MII - M0_TXEN Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M0_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. TBI - M0_TXD[8] Transmit Data. Clocked on rising edge of M0_GTXCLK. GMII/MII - M0_TXER Transmit Error. Transmitted synchronously with respect to M0_TXCLK, and active high. When asserted (with M0_TXEN also asserted) the ZL50118/19/20 will transmit a non-valid symbol, somewhere in the transmitted frame. TBI - M0_TXD[9] Transmit Data. Clocked on rising edge of M0_GTXCLK. GMII/TBI only - Gigabit Transmit Clock Output of a clock for Gigabit operation at 125 MHz.
M0_TXCLK
IU
A3
M0_TXD[7:0]
O
[7] [6] [5] [4] A9
M0_TXEN / M0_TXD[8]
O
M0_TXER / M0_TXD[9]
O
B10
M0_GTX_CLK
O
A8
Table 8 - MII Port 0 Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50118/19/20
MII Port 1 (ZL50118/19/20 only) Signal M1_LINKUP_LED I/O O C17 Package Balls Description
Data Sheet
LED drive for MAC 1 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 1 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off MII only - Receive Clock. Accepts the following frequencies: 25.0 MHz MII 100 Mbps Collision Detection. This signal is independent of M1_TXCLK and M1_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation. E1 D3 [1] [0] D1 D2 Receive Data. Clocked on rising edge of M1_RXCLK. Receive Data Valid. Active high. This signal is clocked on the rising edge of M1_RXCLK. It is asserted when valid data is on the M1_RXD bus. Receive Error. Active high signal indicating an error has been detected. Normally valid when M1_RXDV is asserted. Can be used in conjunction with M1_RXD when M1_RXDV signal is de-asserted to indicate a False Carrier. Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. MII only - Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbps C1 B1 [1] [0] B5 B4 Transmit Data. Clocked on rising edge of M1_TXCLK. Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M1_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high.
M1_ACTIVE_LED
O
B15
M1_RXCLK
IU
C4
M1_COL
ID
C5
M1_RXD[3:0] M1_RXDV
IU ID
[3] [2] D5
M1_RXER
ID
E4
M1_CRS
ID
F2
M1_TXCLK
IU
E3
M1_TXD[3:0] M1_TXEN
O O
[3] [2] A2
Table 9 - MII Port 1 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50118/19/20
MII Port 1 (ZL50118/19/20 only) Signal M1_TXER I/O O C6 Package Balls Description
Data Sheet
Transmit Error. Transmitted synchronously with respect to M1_TXCLK, and active high. When asserted (with M1_TXEN also asserted) the ZL50118/19/20 will transmit a non-valid symbol, somewhere in the transmitted frame.
Table 9 - MII Port 1 Interface Package Ball Definition (continued)
2.4
CPU Interface
All CPU Interface signals are 5 V tolerant. All CPU Interface outputs are high impedance while System Reset is LOW. Signal CPU_DATA[31:0] I/O I/ OT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] Package Balls C16 E19 C18 A11 B16 C19 D20 A12 A14 B17 E20 B18 A16 F20 F21 F22 D21 N20 P22 R22 N22 P21 P20 T22 U21 T21 R21 U22 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] E21 E22 B19 A17 G21 H19 A18 A19 A20 D22 J20 H21 J21 K20 H20 G22 R20 V21 V22 W22 Y22 AA22 AB21 W21 AB20 AB19 Description CPU Data Bus. Bi-directional data bus, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL50118/19/20 device, CPU_DATA[0] is the least significant bit (lsb).
CPU_ADDR[23:2]
I
CPU Address Bus. Address input from processor to ZL50118/19/20, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL50118/19/20 device, CPU_ADDR[2] is the least significant bit (lsb).
Table 10 - CPU Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50118/19/20
Signal CPU_CS I/O IU N21 Package Balls Description
Data Sheet
CPU Chip Select. Synchronous to rising edge of CPU_CLK and active low. Is asserted with CPU_TS_ALE. Must be asserted with CPU_OE to asynchronously enable the CPU_DATA output during a read, including DMA read. CPU Write Enable. Synchronously asserted with respect to CPU_CLK rising edge, and active low. Used for CPU writes from the processor to registers within the ZL50118/19/20. Asserted one clock cycle after CPU_TS_ALE. CPU Output Enable. Synchronously asserted with respect to CPU_CLK rising edge, and active low. Used for CPU reads from the processor to registers within the ZL50118/19/20. Asserted one clock cycle after CPU_TS_ALE. Must be asserted with CPU_CS to asynchronously enable the CPU_DATA output during a read, including DMA read. Synchronous input with rising edge of CPU_CLK. Latch Enable (ALE), active high signal. Asserted with CPU_CS, for a single clock cycle. CPU/DMA 1 Acknowledge Input. Active low synchronous to CPU_CLK rising edge. Used to acknowledge request from ZL50118/19/20 for a DMA write transaction. Only used for DMA transfers, not for normal register access. CPU/DMA 2 Acknowledge Input Active low synchronous to CPU_CLK rising edge. Used to acknowledge request from ZL50118/19/20 for a DMA read transaction. Only used for DMA transfers, not for normal register access. CPU PowerQUICCTM II Bus Interface clock input. 66 MHz clock, with minimum of 6 ns high/low time. Used to time all host interface signals into and out of ZL50118/19/20 device.
CPU_WE
I
M21
CPU_OE
I
M22
CPU_TS_ALE
I
M20
CPU_SDACK1
I
A21
CPU_SDACK2
I
L21
CPU_CLK
I
L19
Table 10 - CPU Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50118/19/20
Signal CPU_TA I/O OT B22 Package Balls Description
Data Sheet
CPU Transfer Acknowledge. Driven from tri-state condition on the negative clock edge of CPU_CLK following the assertion of CPU_CS. Active low, asserted from the rising edge of CPU_CLK. For a read, asserted when valid data is available at CPU_DATA. The data is then read by the host on the following rising edge of CPU_CLK. For a write, is asserted when the ZL50118/19/20 is ready to accept data from the host. The data is written on the rising edge of CPU_CLK following the assertion. Returns to tri-state from the negative clock edge of CPU_CLK following the de-assertion of CPU_CS. CPU DMA 0 Request Output Active low synchronous to CPU_CLK rising edge. Asserted by ZL50118/19/20 to request the host initiates a DMA write. Only used for DMA transfers, not for normal register access. CPU DMA 1 Request Active low synchronous to CPU_CLK rising edge. Asserted by ZL50118/19/20 to indicate packet data is ready for transmission to the CPU, and request the host initiates a DMA read. Only used for DMA transfers, not for normal register access. CPU Interrupt 0 Request (Active Low) CPU Interrupt 1 Request (Active Low)
CPU_DREQ0
OT
K22
CPU_DREQ1
OT
C22
CPU_IREQO CPU_IREQ1
O O
J22 G20
Table 10 - CPU Interface Package Ball Definition (continued)
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Zarlink Semiconductor Inc.
ZL50118/19/20
2.5 System Function Interface
Data Sheet
All System Function Interface signals are 5 V tolerant. The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to allow the PLL's to lock. Signal SYSTEM_CLK I/O I W13 Package Balls Description System Clock Input. The system clock frequency is 100 MHz. The frequency must be accurate to within 32 ppm in synchronous mode. System Reset Input. Active low. The system reset is asynchronous, and causes all registers within the /1/4 to be reset to their default state. System Debug Enable. This is an asynchronous signal that, when de-asserted, prevents the software assertion of the debug-freeze command, regardless of the internal state of registers, or any error conditions. Active high.
SYSTEM_RST
I
AA12
SYSTEM_DEBUG
I
AA11
Table 11 - System Function Interface Package Ball Definition
2.6 2.6.1
Test Facilities Administration, Control and Test Interface
All Administration, Control and Test Interface signals are 5 V tolerant. Signal GPIO[15:0] I/O ID/ OT [15] [14] [13] [12] [11] [10] [9] [8] [2] [1] [0] Package Balls W17 Y16 AB16 AA16 AB15 AB14 W15 Y15 AB17 Y17 AA17 [7] [6] [5] [4] [3] [2] [1] [0] AA15 AB13 AB12 AB11 AB10 AA14 AA13 AB9 Description General Purpose I/O pins. Connected to an internal register, so customer can set user-defined parameters. Bits [4:0] reserved at start-up or reset for memory TDL setup. See the ZL50118/19/20 Programmers Model for more details.
TEST_MODE[2:0]
ID
Test Mode input - ensure these pins are tied to ground for normal operation. 000 SYS_NORMAL_MODE 001-010 RESERVED 011 SYS_TRISTATE_MODE 100-111 RESERVED
Table 12 - Administration/Control Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50118/19/20
2.6.2 JTAG Interface
Data Sheet
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001). Signal JTAG_TRST JTAG_TCK I/O IU I Y18 V20 Package Balls Description JTAG Reset. Asynchronous reset. In normal operation this pin should be pulled low. JTAG Clock - maximum frequency is 25MHz, typically run at 10 MHz. In normal operation this pin should be pulled either high or low. JTAG test mode select. Synchronous to JTAG_TCK rising edge. Used by the Test Access Port controller to set certain test modes. JTAG test data input. Synchronous to JTAG_TCK. JTAG test data output. Synchronous to JTAG_TCK.
JTAG_TMS
IU
U20
JTAG_TDI JTAG_TDO
IU O
AA18 W20
Table 13 - JTAG Interface Package Ball Definition
2.7
Miscellaneous Inputs
The following unused inputs must be tied low or high as appropriate. Signal IC_GND IC_VDD_IO L22 Package Balls W11, Y11, Y19, AA19, AB18 Description Internally connected. Tie to GND. Internally connected. Tie to VDD_IO.
Table 14 - Miscellaneous Inputs Package Ball Definitions
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Zarlink Semiconductor Inc.
ZL50118/19/20
2.8 Power and Ground Connections
Signal VDD_IO A1 AA4 B2 C20 D4 K4 T19 W16 W7 A13 AA7 B3 J10 J14 K12 K9 L12 L9 M13 N10 N14 P12 P9 Y13 D14 F19 J4 P4 W9 AA8 Package Balls A22 AA5 B21 C3 D7 M4 T20 W19 W8 A15 AB5 C2 J11 J9 K13 L1 L13 M10 M14 N11 N9 P13 R19 Y14 D15 F4 L4 U19 Y6 AA2 AB1 C14 D16 G19 N19 T4 W4 Y20 AA20 B11 C21 J12 K10 K14 L10 L14 M11 M19 N12 P10 P14 U3 Y2 D18 H4 N4 W14 AA21 AB22 C15 D19 G4 P3 U2 W5 Y3 AA3 B20 H2 J13 K11 K19 L11 L20 M12 M9 N13 P11 P2 W12 Y21 D9 J19 P19 W6 Description
Data Sheet
3.3 V VDD Power Supply for IO Ring
GND
0 V Ground Supply
VDD_CORE
1.8 V VDD Power Supply for Core Region
A1VDD
1.8 V PLL Power Supply Table 15 - Power and Ground Package Ball Definition
37
Zarlink Semiconductor Inc.
ZL50118/19/20
2.9 Internal Connections
Data Sheet
The following pins are connected internally, and must be left open circuit. Signal IC AA1 AB2 AB7 W1 Y4 Package Balls AA10 AB3 AB8 Y1 Y5 AA6 AB4 H22 Y10 Y7 AA9 AB6 K21 Y12 Y8 Description Internally connected. Leave open circuit
Table 16 - Internal Connections Package Ball Definitions
2.10
No Connections
The following pins are not connected internally, and should be left open circuit. Signal NC F1 J3 Package Balls H3 K1 J1 K2 J2 K3 Description No connection. Leave open circuit.
Table 17 - Miscellaneous Inputs Package Ball Definitions
2.11
Device ID
Signal I/O O [4] [3] [2] [1] [0] Package Balls A10 V19 W18 F3 G2 Description Device ID. ZL50118 = 00011 ZL50119 = 00100 ZL50120 = 00101
DEVICE_ID[4:0]
Table 18 - Device ID Ball Definition
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Zarlink Semiconductor Inc.
ZL50118/19/20
3.0
3.1
Data Sheet
Typical Applications
Leased Line Provision
Circuit emulation is typically used to support the provision of leased line services to customers using legacy TDM equipment. For example, Figure 4 shows a leased line TDM service being carried across a packet network. The advantages are that a carrier can upgrade to a packet switched network, whilst still maintaining their existing TDM business. The ZL50118/19/20 is capable of handling circuit emulation of both structured T1, E1, and J2 links (e.g., for support of fractional circuits) and unstructured (or clear channel) T1, E1, J2, T3 and E3 links. The device handles the data-plane requirements of the provider edge inter-working function (with the exception of the physical interfaces and line interface units). Control plane functions are forwarded to the host processor controlling the ZL50118/19/20 device. The ZL50118/19/20 provides a per-stream clock recovery function to reproduce the TDM service frequency at the egress of the packet network. This is required otherwise the queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original.
Customer Premises
Customer data
Carrier Network
Customer Premises
queue
TDM
TDM to packet
Packet Network
TDM fservice
fservice
Provider Edge Interworking Function
~
~
fservice
Provider Edge Interworking Function
Extract Clock
Figure 4 - Leased Line Services Over a Circuit Emulation Link
39
Zarlink Semiconductor Inc.
Customer data
ZL50118/19/20
3.2 Remote Concentrator Unit
Data Sheet
The remote concentrator application, shown in Figure 5, consists of a remote concentrators connected to the Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) or Ethernet over SONET (EoS) rather than by NxT1/E1 or DS3/E3. The remote concentrators provide both TDM service and native Ethernet service to the Multi-Tenet Unit or Multi-Dwelling Unit (MTU/MDU). The ZL50118/19/20 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between the remote concentrator and the CO. The native IP or Ethernet traffic is multiplexed with the CESoP traffic inside the remote concentrator and sent across the same GE connection to the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections from several remote concentrators are aggregated in the CO using a larger ZL50118/19/20 variant, converted back to TDM circuits, and connected to the PSTN through a higher bandwidth TDM circuit such as OC-3 or STM-1. The use of CESoP here allows the convergence of voice and data on a single access network based on Ethernet. This convergence on Ethernet, a packet technology, rather than SONET/SDH, a switched circuit technology, provides cost and operational savings.
Figure 5 - Remote Concentrator Unit using CESoP
40
Zarlink Semiconductor Inc.
ZL50118/19/20
3.3 FTTP
Data Sheet
The Fiber to the Premise (FTTP) application, shown in Figure 6, consists of an Ethernet Passive Optical Network (EPON) deployed in the Wide Area Network (WAN). The Optical Network Units (ONU) sit at the curb while the Optical Line Terminals (OLT) are located at the Central Office (CO). The ONUs are traditionally equipped with Ethernet interfaces to provide video and data service to the customer premise. The ONU includes a ZL50118/19/20 which enables the box to provide T1/E1 service to the customer. The ZL50118/19/20 is used to establish CESoP connections between the ONU and the OLT to transparently carry TDM circuits across the EPON. The ONU would use a smaller variant of the ZL50118/19/20 and the OLT would use a larger variant to aggregate CESoP traffic from many ONUs and connect them at the CO to the PSTN. The native IP or Ethernet traffic from the ONU would be split off at the OLT and connected to the packet network.
Customer Premises
Ethernet Fiber Links T1/E1
ONU
Ethernet GIGE Over Fiber
IP
Ethernet T1/E1
ONU
Optical Splitter
OLT
T1/E1
Ethernet T1/E1
PSTN
ONU
CESoP
Figure 6 - EPON using CESoP
41
Zarlink Semiconductor Inc.
ZL50118/19/20
3.4 Wireless - WiFi or WiMAX
Data Sheet
The wireless application, shown in Figure 7, may either be in the form of WiMAX for broadband access or Wi-Fi for smaller-scale Loans. Both technologies carry Ethernet over radio links between sites or pieces of equipment. An application for CESoP technology over a WiMAX network is to enable the service provider to sell T1/E1 service in addition to video and data services that are natively carried across the WiMAX connection. A ZL50118/19/20 is used at the customer premise to packetize the T1/E1, fractional T1/E1 or TDM circuit into Ethernet packets, which are transported back to the Central Office (CO). At the CO the TDM circuit is re-assembled from the Ethernet packets and send to the PSTN. The CESoP traffic is converged onto the same WiMAX connection as the native Ethernet traffic for video and data. An application for CESoP technology over a Wi-Fi network is to enable a distributed PBX system in either a single building or between buildings in a campus environment. In this application the T1/E1 connection from a PBX is connected using a CESoP to another PBX. A wireless site-to-site CESoP connection between buildings in a campus would allow for deployment savings against having to run dedicated copper cables between buildings.
Wireless LAN Access Point
WiMAX (802.16)
Wireless LAN Access Point T1/E1 CESoP WiMAX MAC 70 Mbps Up to 48 Km
WiMAX MAC
CESoP T1/E1
CESoP
Wi-Fi (802.11)
Wireless LAN Access Point T1/E1 CESoP Wi-Fi MAC 54 Mbps Up to 100 m Wireless LAN Access Point Wi-Fi MAC CESoP T1/E1
CESoP
Figure 7 - Wi-Fi and WiMAX using CESoP
42
Zarlink Semiconductor Inc.
ZL50118/19/20
3.5 Digital Loop Carrier
Data Sheet
The Broadband Digital Loop Carrier (BBDLC) application, shown in Figure 8, consists of a BBDLC connected to the Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) rather than by NxT1/E1 or DS3/E3. The ZL50118/19/20 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between the BBDLC and the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections from several BBDLC are aggregated in the CO using a larger ZL50118/19/20 variant, converted back to TDM circuits, and connected to a class 5 switch destined towards the PSTN. In this configuration T3/E3 services can also be provided. Using CESoP allows voice and data traffic to be converged onto a single link.
IP Edge Router or Multi-Service Switching Platform N x GIGE
POTS Digital Loop Carrier
GIGE Over Fiber
IP
Dedicated Fiber Links
T1/E1 Broadband DLC
GIGE Over Fiber
Central Office
N x T1/E1
Central Office Switch (Class 5)
PSTN
CESoP
Figure 8 - Digital Loop Carrier using CESoP
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3.6 Integrated Access Device
Data Sheet
The Integrated Access Device (IAD) application consists of an IAD located at the curb or customer premise with an Ethernet connection to an TDM aggregation box sitting in the access area of the network. The ZL50118/19/20 in the IAD modem packetizes the T1/E1 or fractional T1/E1 TDM circuit into Ethernet CESoP packets. The CESoP traffic is multiplexed with the native Ethernet data traffic from the IAD's Ethernet ports onto the Ethernet link to the aggregation equipment. The aggregator will split off the native Ethernet traffic from multiple IADs and send the traffic on to packet network. The aggregator will contain a larger ZL50118/19/20 that will terminate multiple CESoP connections from multiple IADs and send the TDM circuits to the PSTN, perhaps over a higher bandwidth TDM pipe such as DS3. The use of CESoP in this application allows the IAD to support both native Ethernet service as well as T1/E1 service in the same box, while converging both types of traffic onto a single Ethernet connection back towards the provider.
Small business
Ethernet T1/E1 N x GIGE
IP Edge Router or Multi-Service Switching Platform
IAD
Ethernet link
IP
Small business
Ethernet T1/E1
TDM Aggregation
Central Office Switch (Class 5)
IAD
Ethernet link
N x T1/E1
PSTN
CESoP
Figure 9 - Integrated Access Device Using CESoP
4.0
Functional Description
The ZL50118/19/20 family provides the data-plane processing to enable constant bit rate TDM services to be carried over a packet switched network, such as an Ethernet, IP or MPLS network. The device segments the TDM data into user-defined packets, and passes it transparently over the packet network to be reconstructed at the far end. This has a number of applications, including emulation of TDM circuits and packet backplanes for TDM-based equipment.
Transparent data flow between TDM equipment
TDM equipment
constant bit rate TDM link
CESoP TDM-Packet conversion
interworking function
packet switched network
CESoP TDM-Packet conversion
interworking function
TDM equipment
constant bit rate TDM link
Figure 10 - ZL50118/19/20 Family Operation
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4.1 Block Diagram
Data Sheet
A diagram of the ZL50118/19/20 device is given in Figure 11, which shows the major data flows between functional components.
Motorola PowerQUICC
TM
Compatible
DMA Control
Host Interface
Admin.
Payload Assembly TDM Interface TDM Formatter
Central Task Manager
Packet Transmit
Protocol Engine
Packet Receive
Dual Packet Interface MAC
Clock Recovery
Memory Management Unit On-chip RAM Controller
JTAG Test Controller
Data Flows Control Flows
JTAG Interface
Figure 11 - ZL50118/19/20 Data and Control Flows
4.2
Data and Control Flows
There are numerous combinations that can be implemented to pass data through the ZL50118/19/20 device depending on the application requirements. The Task Manager can be considered the central pivot, through which all flows must operate. The Task Manager acts as a "router" in the centre of the chip, directing packets to the appropriate blocks for further processing. The task message contains a pointer to the relevant data, instructions as to what to do with the data, and ancillary information about the packet. Effectively this means the flow of data through the device can be programmed, by setting the task message contents appropriately. Flow Number 1 2 3 4 5 6 7 8 9 10 11
1 1
Flow Through Device TDM to (TM) to PE to (TM) to PKT PKT to (TM) to PE to (TM) to TDM TDM to (TM) to PKT PKT to (TM) to TDM TDM to (TM) to CPU TDM to (TM) to PE to (TM) to CPU CPU to (TM) to TDM PKT to (TM) to CPU CPU to (TM) to PKT TDM to (TM) to TDM PKT to (TM) to PKT
Table 19 - Standard Device Flows
1. This flow is for loopback and may be helpful for test purposes
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Zarlink Semiconductor Inc.
Single 100 Mbps MII Fast Ethernet and Single 1000 Mbps (G)MII/TBI Gigabit Ethernet
4 T1, 4 E1, 1 J2, 1 T3, 1 E3 or 1 STS-1 ports H.110, H-MVIP, ST-BUS backplanes
ZL50118/19/20
Data Sheet
Each of the 11 data flows uses the Task Manager to route packet information to the next block or interface for onward transmission. The flow is determined by the Type field in the Task Message (see ZL50118/19/20 Programmers Model).
4.3
TDM Interface
The ZL50118/19/20 family offers the following types of TDM service across the packet network: Service type Unstructured asynchronous Structured synchronous (N x 64 Kbps) TDM interface T1, E1, J2, E3, T3 and STS-1 T1, E1 and J2 Framed TDM data streams at 2.048 and 8.192 Mbps Interface type Bit clock in and out Data in and out Bit clock out Frame pulse out Data in and out Bit clock in Frame in Data in and out Interfaces to Line interface unit Framers TDM backplane (master) Framers TDM backplane (slave)
Table 20 - TDM Services Offered by the ZL50118/19/20 Family Unstructured services are fully asynchronous, and include full support for clock recovery on a per stream basis. Both adaptive and differential clock recovery mechanisms can be used. Structured services are synchronous, with all streams driven by a common clock and frame reference. These services can be offered in two ways: * * Synchronous master mode - the ZL50118/19/20 provides a common clock and frame pulse to all streams, which may be locked to an incoming clock or frame reference Synchronous slave mode - the ZL50118/19/20 accepts a common external clock and frame pulse to be used by all streams
In either structured mode, N x 64 Kbps trunking is supported as detailed in "Payload Order" on page 50.
4.3.1
TDM Interface Block
The TDM Interface contains two basic types of interface: unstructured clock and data, for interfacing directly to a line interface unit; or structured, framed data, for interfacing to a framer or TDM backplane. Unstructured data is treated asynchronously, with every stream using its own clock. Clock recovery is provided on each output stream, to reproduce the TDM service frequency at the egress of the packet network. Structured data is treated synchronously, i.e. all data streams are timed by the same clock and frame references. These can either be supplied from an external source (slave mode) or generated internally using the on-chip stratum 3/4/4E PLL (master mode).
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4.3.2 Structured TDM Port Data Formats
Data Sheet
The ZL50118/19/20 is programmable such that the frame/clock polarity and clock alignment can be set to any desired combination. Table 21 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and Generic (synchronous mode only), for more information see the relevant specifications shown. There are many additional formats for TDM transmission not depicted in Table 21, but the flexibility of the port will cover almost any scenario. The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format (used when operating in synchronous master mode). Number of channels per frame 32 32 128 128 32 32 128 32 Nominal Frame Pulse Width (ns) ST-bus 2.048 2.048 8.192 H.110 H-MVIP 8.192 2.048 2.048 8.192 Generic 2.048 2.048 4.096 16.384 8.192 2.048 4.096 16.384 2.048 244 244 61 122 244 244 244 488 Negative Negative Negative Negative Negative Negative Negative Positive Rising Edge Falling Edge Falling Edge Rising edge Rising Edge Falling Edge Falling Edge Rising Edge Rising Edge Frame Boundary Alignment Standard clock frame pulse Straddles boundary Straddles boundary Straddles boundary Straddles boundary Straddles boundary Straddles boundary Straddles boundary Rising edge of clock Rising edge of clock ECTF H.110 H-MVIP Release 1.1a MSAN-126 Rev B (Issue 4) Zarlink
Data Format
Data Rate (Mbps)
Clock Freq. (MHz)
Frame Pulse Polarity
8.192
128
8.192
122
Positive
Table 21 - Some of the TDM Port Formats Accepted by the ZL50118/19/20 Family
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Zarlink Semiconductor Inc.
ZL50118/19/20
4.3.3 TDM Clock Structure
Data Sheet
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for unstructured TDM data. The ZL50118/19/20 is capable of providing the TDM clock for either of the modes, but clock recovery is only possible in asynchronous mode, where the timing for each stream is controlled independently.
4.3.3.1
Synchronous TDM Clock Generation
In synchronous mode all 4 streams will be driven by a common clock source. When the ZL50118/19/20 is acting as a master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary and secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to the chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the output pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse required to drive the TDM streams. See "DPLL Specification" on page 58 for further details.
TDM_CLKi[3:0]
PRS
PRD
PLL_PRI PLL_SE C
DIV TDM_CLKiP SRS SRD
CLOCK
TDM_CLKiS
DIV
Internal DPLL
FRAME
Figure 12 - Synchronous TDM Clock Generation When the ZL50118/19/20 is acting as a slave device, the common clock and frame pulse signals are taken from an external device providing the TDM master function.
4.3.3.2
Asynchronous TDM Clock Generation
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be controlled to recover the clock from the original TDM source depending on the timing algorithm used.
4.4
Payload Assembly
Data traffic received on the TDM Interface is sampled in the TDM Interface block, and synchronized to the internal clock. It is then forwarded to the payload assembly process. The ZL50118/19/20 Payload Assembler can handle up to 128 active packet streams or "contexts" simultaneously. Each context generates a single stream of packets identified by a label in the packet header known as the "context ID". Packet payloads are assembled in the format shown in Figure 13 on page 49 in structured operation. This meets the requirements of the CESoPSN standard under development in the IETF. Alternatively, packet payloads are assembled in the format shown in Figure 15 on page 50. This format meets the requirements of the SAToP standard under development in the IETF. When the payload has been assembled it is written into the centrally managed memory, and a task message is passed to the Task Manager.
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4.4.1 Structured Payload Operation
Data Sheet
In structured mode a context may contain any number of 64 kbps channels. These channels need not be contiguous and they may be selected from any input stream. Channels may be added or deleted dynamically from a context. This feature can be used to optimize bandwidth utilisation. Modifications to the context are synchronised with the start of a new packet. The fixed header at the start of each packet is added by the Packet Transmit block. This consists of up to 64 bytes, containing the Ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see section below). The header is entirely user programmable, enabling the use of any protocol. The payload header and size must be chosen so that the overall packet size is not less than 64 bytes, the Ethernet standard minimum packet size. Where this is likely to be the case, the header or data must be padded (as shown in Figure 13 and Figure 15) to ensure the packet is large enough. This padding is added by the ZL50118/19/20 for most applications.
Ethernet Header Header
(added by Packet Transmit)
may include VLAN tagging e.g. IPv4, IPv6, MPLS e.g. UDP, L2TP, RTP, CESoPSN, SAToP
Network Layers Upper layers
(added by Protocol Engine)
Data for TDM Frame 1
Channel 1 Channel 2 Channel x Channel 1 Channel 2 Channel x TDM Payload
(constructed by Payload Assembler)
Data for TDM Frame 2
Data for TDM Frame n
Channel 1 Channel 2 Channel x Static Padding
(if required to meet minimum payload size) may also be placed in the packet header
Ethernet FCS
Figure 13 - ZL50118/19/20 Packet Format - Structured Mode In applications where large payloads are being used, the payload size must be chosen such that the overall packet size does not exceed the maximum Ethernet packet size of 1518 bytes (1522 bytes with VLAN tags). Figure 13 shows the packet format for structured TDM data, where the payload is split into frames, and each frame concatenated to form the packet.
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4.4.1.1 Payload Order
Data Sheet
Packets are assembled sequentially, with each channel placed into the packet as it arrives at the TDM Interface. A fixed order of channels is maintained (see Figure 14), with channel 0 placed before channel 1, which is placed before channel 2. It is this order that allows the packet to be correctly disassembled at the far end. A context must contain only unique channel numbers. As such a context that contains the same channel from different streams, for example channel 1 from stream 2 and channel 1 from stream 3, would not be permitted.
S tre a m 0
C hannel 0
C hannel 1
C hannel 2
C hannel 31
S tre a m 1
C hannel 0
C hannel 1
C hannel 2
C hannel 31
S tre a m 2
C hannel 0
C hannel 1
C hannel 2
C hannel 31
S tre a m 3
C hannel 0
C hannel 1
C hannel 2 C h a n n e l A s se m b ly O rd e r
C hannel 31
Figure 14 - Channel Order for Packet Formation Each packet contains one or more frames of TDM data, in sequential order. This groups the selected channels for the first frame, followed by the same set of channels for the subsequent frame, and so on.
4.4.2
Unstructured Payload Operation
In unstructured mode, the payload is not split by defined frames or timeslots, so the packet consists of a continuous stream of data. Each packet consists of a number of octets, as shown in Figure 15. The number of octets in a packet need not be an integer number of frames. A typical value for N may be 192, as defined in the IETF PWE3 standard." For example, consider mapping the unstructured data of a 25 timeslot DS0 stream. The data for each T1 frame would normally consist of 193 bits, 192 data bits and 1 framing bit. If the payload consists of 24 octets it will be 1 bit short of a complete frames worth of data, if the payload consists of 25 octets it will be 7 bits over a complete frames worth of data. NOTE: No alignment of the octets with the T1 framing structure can be assumed.
Ethernet Header
Header
Network Layers
(added by Packet Transmit)
Upper layers
(added by Protocol Engine)
may include VLAN tagging e.g. IPv4, IPv6, MPLS e.g. UDP, L2TP, RTP, CESoPSN, SAToP
N octets of data from unstructured stream NOTE: No frame or channel alignment
Octet 1 Octet 2 Octet N Static Padding Ethernet FCS
TDM Payload (constructed by Payload Assembler) 46 to 1500 bytes may also be placed in the
(if required to meet minimum payload size) packet header
Figure 15 - ZL50118/19/20 Packet Format - Unstructured Mode
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Zarlink Semiconductor Inc.
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4.5 Protocol Engine
Data Sheet
In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the ZL50118/19/20 family: UDP, RTP, L2TP, CESoPSN, SAToP and CDP. The Protocol Engine can add a header to the datagram containing up to 24 bytes. This header is largely static information, and is programmed directly by the CPU. It may contain a number of dynamic fields, including a length field, checksum, sequence number and a timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various protocols to be placed at variable locations within the header.
4.6
Packet Transmission
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet Transmit block appends a programmable header, which has been set up in advance by the control processor. Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP (versions 4 and 6) and MPLS.
4.7
Packet Reception
Incoming data traffic on the packet interface is received by the MACs. The well-formed packets are forwarded to a packet classifier to determine the destination. When a packet is successfully classified the destination can be the TDM interface, the LAN interface or the host interface. TDM traffic is then further classified to determine the context it is intended for. Each TDM interface context has an individual queue, and the TDM re-formatting process re-creates the TDM streams from the incoming packet streams. This queue is used as a jitter buffer, to absorb variation in packet delay across the network. The size of the jitter buffer can be programmed in units of TDM frames (i.e., steps of 125 s). There is also a queue to the host interface, allowing a traffic flow to the host CPU for processing. The host's DMA controller can be used to retrieve packet data and write it out into the CPU's own memory.
4.8
TDM Formatter
At the receiving end of the packet network, the original TDM data must be re-constructed from the packets received. This is known as re-formatting, and follows the reverse process from the Payload Assembler. The TDM Formatter plays out the packets in the correct sequence, directing each octet to the selected timeslot on the output TDM interface. When lost or late packets are detected, the TDM Formatter plays out underrun data for the same number of TDM frames as were included in the missing packet. Underrun data can either be the last value played out on that timeslot, or a pre-programmed value (e.g., 0xFF). If the packet subsequently turns up it is discarded. In this way, the end-to-end latency through the system is maintained at a constant value.
4.9
Ethernet Traffic Aggregation
The ZL50118/19/20 allows native Ethernet traffic received on the customer side Fast Ethernet port to be aggregated with the CESoP traffic from the TDM interface to the provider side Gigabit Ethernet port. Likewise, traffic from the provider side Gigabit Ethernet port may be split between CESoP traffic destined towards the TDM interface and native Ethernet traffic destined towards the customer side Fast Ethernet port. This functionality is achieved by correctly programming the task manager and packet classifiers for flow 11. From the provider side Gigabit Ethernet port to the customer side TDM and Fast Ethernet interfaces there is sufficient internal bandwidth to avoid any prioritization issues. From the customer side TDM and Fast Ethernet interfaces towards the Gigabit Ethernet ports the TDM CESoP traffic may be sent to a higher priority output queue (there are four output queues total) than the native Fast Ethernet traffic. In this way the access to the provider side Gigabit Ethernet port is prioritized for TDM traffic over native Ethernet traffic.
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5.0 Clock Recovery
Data Sheet
One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked into the central office reference clock, and hence may be any value within the tolerance defined for that service. The reverse link may also be independently timed, and operating at a slightly different frequency. In the plesiochronous digital hierarchy the difference in clock frequencies between TDM links is compensated for using bit stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network. With a packet network, that connection between the ingress and egress frequency is broken, since packets are discontinuous in time. From Figure 4, the TDM service frequency fservice at the customer premises must be exactly reproduced at the egress of the packet network. The consequence of a long-term mismatch in frequency is that the queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original. This will cause loss of data and degradation of the service. The ZL50118/19/20 provides a per-stream clock recovery function to reproduce the TDM service frequency at the egress of the packet network. There are two schemes are employed, depending on the availability of a common reference clock at each provider edge unit, within the ZL50118/19/20 - differential and adaptive. The clock recovery itself is performed by software in the external processor, with support from on-chip hardware to gather the required statistics.
5.1
Differential Clock Recovery
For applications where the wander characteristics of the recovered clock are very important, such as when the emulated circuit must be connected into the plesiochronous digital hierarchy (PDH), the ZL50118/19/20 also offers a differential clock recovery technique. This relies on having a common reference clock available at each provider edge point. Figure 16 illustrates this concept with a common Primary Reference Source (PRS) clock being present at both the source and destination equipment. In a differential technique, the timing of the TDM service clock is sent relative to the common reference clock. Since the same reference is available at the packet egress point and the packet size is fixed, the original service clock frequency can be recovered. This technique is unaffected by any low frequency components in the packet delay variation. The disadvantage is the requirement for a common reference clock at each end of the packet network, which could either be the central office TDM clock, or provided by a global position system (GPS) receiver.
PRS clock
Data
ZL5011x source node
Packets
ZL5011x destination node Network
Packets
Data
LIU
Source Clock
Timestamp generation
Timestamp extraction DCO
Dest'n Clock
LIU
Host CPU Timing recovery
Figure 16 - Differential Clock Recovery
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Zarlink Semiconductor Inc.
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5.2 Adaptive Clock Recovery
Data Sheet
For applications where there is no common reference clock between provider edge units, an adaptive clock recovery technique is provided. This infers the clock rate of the original TDM service clock from the mean arrival rate of packets at the packet egress point. The disadvantage of this type of scheme is that, depending on the characteristics of the packet network, it may prove difficult to regenerate a clock that stays within the wander requirements of the plesiochronous digital hierarchy (specifically MTIE). The reason for this is that any variation in delay between packets will feed through as a variation in the frequency of the recovered clock. High frequency jitter can be filtered out, but any low frequency variation or wander is more difficult to remove without a very long time constant. This will in turn affect the ability of the system to lock to the original clock within an acceptable time. With no PRS clock the only information available to determine the TDM transmission speed is the average arrival rate of the packets, as shown in Figure 17. Timestamps representing the number of elapsed source clock periods may be included in the packet header, or information can be inferred from a known payload size at the destination. It is possible to maintain average buffer-fill levels at the destination, where an increase or decrease in the fill level of the buffer would require a change in transmission clock speed to maintain the average. Additionally, the buffer-fill depth can be altered independently, with no relation to the recovered clock frequency, to control TDM transmission latency.
Data
ZL5011x source node
Packets
ZL5011x destination node Network
Packets
Data
LIU
Source Clock
Dest'n Clock
LIU
DCO
Host CPU Queue monitor
Figure 17 - Adaptive Clock Recovery
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Zarlink Semiconductor Inc.
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6.0
6.1
Data Sheet
System Features
Latency
The following lists the intrinsic processing latency of the ZL50118/19/20, regardless of the number of active channels or contexts. * * * * TDM to Packet transmission processing latency less than 125 s Packet to TDM transmission processing latency less than 250 s (unstructured) Packet to TDM transmission processing latency less than 250 s (structured, more than 16 channels in context) Packet to TDM transmission processing latency less than 375 s (structured, 16 or less channels in context)
End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The transmit latency is the sum of the transmit processing and the number of frames per packet x 125 s. The receive latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to compensate for packet network PDV. The ZL50118/19/20 is capable of creating an extremely low latency connection, with end to end delays of less than 0.5 ms, depending on user configuration.
6.2
Loopback Modes
The ZL50118/19/20 devices support loopback of the TDM circuits and the circuit emulation packets. TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM Formatter and TDM Interface. Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks, back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new header directing the packets back to the source.
6.3
Host Packet Generation
The control processor can generate packets directly, allowing it to use the network for out-of-band communications. This can be used for transmission of control data or network setup information, e.g., routing information. The host interface can also be used by a local resource for network transmission of processed data. The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own DMA controller. Table 22 illustrates the maximum bandwidths achievable by an external DMA master. DMA Path ZL50118/19/20 to CPU only ZL50118/19/20 to CPU only CPU to ZL50118/19/20 only CPU to ZL50118/19/20 only Packet Size >1000 bytes 60 bytes >1000 bytes 60 bytes Max Bandwidth Mbps1 50 6.7 60 43
Table 22 - DMA Maximum Bandwidths
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Zarlink Semiconductor Inc.
ZL50118/19/20
DMA Path Combined2 Combined2
Note 1: Note 2:
Data Sheet
Max Bandwidth Mbps1 58 (29 each way) 11 (5.5 each way)
Packet Size >1000 bytes 60 bytes
Table 22 - DMA Maximum Bandwidths (continued)
Maximum bandwidths are the maximum the ZL50118/19/20 devices can transfer under host control, and assumes only minimal packet processing by the host. Combined figures assume the same amount of data is to be transferred each way.
6.4
Loss of Service (LOS)
During normal transmission a situation may arise where a Loss of Service occurs, caused by a disruption in the transmission line due to engineering works or cable disconnection for example. This results in the loss of a TDM signal, including the associated TDM clock, from the LIU. With no TDM signal or clock, no packets can be assembled by the transmitting ZL50118/19/20 device, and the flow of packets will cease. The absence of packets at the receiving ZL50118/19/20 device will cause underrun data to be generated at the TDM output, normally an "all-ones" pattern, with the exception of DS3 which alternates ones and zeros. The LOS condition is detected by the receive ZL50118/19/20 device. Additionally, when the LIU detects LOS, it can notify the CPU. The CPU can set a control bit in the packet header (bit L in the IETF drafts), which is then transmitted. The receiving ZL50118/19/20 device recognizes the control bit, and transmits an AIS (all-ones) pattern on the appropriate TDM stream. Using both mechanisms provides a robust method of indicating an LOS condition to the downstream TDM equipment.
6.5
Power Up sequence
To power up the ZL50118/19/20 the following procedure must be used: * * * The Core supply must never exceed the I/O supply by more than 0.5VDC Both the Core supply and the I/O supply must be brought up together The System Reset and, if used, the JTAG Reset must remain low until at least 100 s after the 100 MHz system clock has stabilised. Note that if JTAG Reset is not used it must be tied low
This is illustrated in the diagram shown in Figure 18.
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Zarlink Semiconductor Inc.
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I/O supply (3.3 V)
Data Sheet
VDD
<0.5 VDC
Core supply (1.8 V)
t
RST
t
> 100 s
SCLK
t
10 ns
Figure 18 - Powering Up the ZL50118/19/20
6.6
JTAG Interface and Board Level Test Features.
The JTAG interface is used to access the boundary scan logic for board level production testing.
6.7
* * *
External Component Requirements
Direct connection to PowerQUICCTM II (MPC8260) host processor and associated memory, but can support other processors with appropriate glue logic TDM Framers and/or Line Interface Units Ethernet PHY for each MAC port
6.8
* * * * * * *
Miscellaneous Features
System clock speed of 100 MHz Host clock speed of up to 66 MHz Debug option to freeze all internal state machines JTAG (IEEE1149) Test Access Port 3.3 V I/O Supply rail with 5 V tolerance 1.8 V Core Supply rail Fully compatible with MT90880/1/2/3 and ZL50110/11/14 Zarlink product line
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6.9 6.9.1 Test Modes Operation Overview
Data Sheet
The ZL50118/19/20 family supports the following modes of operation.
6.9.1.1
System Normal Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access Port and Boundary Scan Architecture. Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
6.9.1.2
System Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the development board.
6.9.2
Test Mode Control
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 23. System Test Mode SYS_NORMAL_MODE SYS_TRI_STATE_MODE test_mode[2:0] 3'b000 3'b011
Table 23 - Test Mode Control
6.9.3
System Normal Mode
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins may be configured by the ADM module as either inputs or outputs.
6.9.4
System Tri-state Mode
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
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7.0 DPLL Specification
Data Sheet
The ZL50118/19/20 family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 3 and Stratum 4/4E requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and MTIE requirements for these specifications. In structured mode with the ZL50118/19/20 device operating as a master the DPLL is used to provide clock and frame reference signals to the internal and external TDM infrastructure. In structured mode, with the ZL50118/19/20 device operating as a slave, the DPLL is not used. All TDM clock generation is performed externally and the input streams are synchronised to the system clock by the TDM interface. The DPLL is not required in unstructured mode, where TDM clock and frame signals are generated by internal DCO's assigned to each individual stream.
7.1
Modes of Operation
It can be set into one of four operating modes: Locking mode, Holdover mode, Freerun mode and Powerdown mode.
7.1.1
Locking Mode (normal operation)
The DPLL accepts a reference signal from either a primary or secondary source, providing redundancy in the event of a failure. These references should have the same nominal frequencies but do not need to be identical as long as their frequency offsets meet the appropriate Stratum requirements. Each source is selected from any one of the available TDM input stream clocks (up to 4 on the ZL50120 variant), or from the external TDM_CLKiP (primary) or TDM_CLKiS (secondary) input pins, as illustrated in Figure 12 - on page 48. It is possible to supply a range of input frequencies as the DPLL reference source, depicted in Table 24. The PRD register Value is the number (in hexadecimal) that must be programmed into the PRD register within the DPLL to obtain the divided down frequency at PLL_PRI or PLL_SEC. Maximum Acceptable Input Wander tolerance (UI) (Note 2) 1 1023 1023 1023 1023 1023 1023 1 (on 64k Hz) 1 (on 64 kHz) 1 (on 64 kHz)
Source Input Frequency (MHz) 0.008 1.544 2.048 4.096 8.192 16.384 6.312 22.368 34.368 44.736 (Note 3)
Note 1: Note 2: Note 3:
Tolerance (ppm)
Divider Ratio
PRD/SRD Register Value (Hex) (Note 1) 1 1 1 1 1 1 1 AEC 219 2BB
Frequency at PLL_PRI or PLL_SEC (MHz) 0.008 1.544 2.048 4.096 8.192 16.384 6.312 0.008 0.064 0.064
30 130 50 50 50 50 30 20 20 20
1 1 1 1 1 1 1 2796 537 699
Table 24 - DPLL Input Reference Frequencies
A PRD/SRD value of 0 will suppress the clock, and prevent it from reaching the DPLL. UI means Unit Interval - in this case periods of the time signal. So 1UI on a 64 kHz signal means 15.625 s, the period of the reference frequency. Similarly 1023UI on a 4.096 MHz signal means 250 s. This input frequency is supported with the use of an external divide by 2.
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Data Sheet
The maximum lock-in range can be programmed up to 372 ppm regardless of the input frequency. The DPLL will fail to lock if the source input frequency is absent, if it is not of approximately the correct frequency or if it is too jittery. See Section 7.7 for further details. Limitations depend on the users programmed values, so the DPLL must be programmed properly to meet Stratum 3, or Stratum 4/4E. The Application Program Interface (API) software that accompanies the ZL50118/19/20 family can be used to automatically set up the DPLL for the appropriate standard requirement. The DPLL lock-in range can be programmed using the Lock Range register (see ZL50118/19/20 Programmers Model document) in order to extend or reduce the capture envelope. The DPLL provides bit-error-free reference switching, meeting the specification limits in the Telcordia GR-1244-CORE standard. If Stratum 3 or Stratum 4/4E accuracy is not required, it is possible to use a more relaxed system clock tolerance. The DPLL output consists of three signals; a common clock (comclk), a double-rate common clock (comclkx2) and a frame reference (8 kHz). These are used to time the internal TDM Interface, and hence the corresponding TDM infrastructure attached to the interface. The output clock options are either 2.048 Mbps (comclkx2 at 4.096 Mbps) or 8.192 Mbps (comclkx2 at 16.384 Mbps), determined by setup in the DPLL control register. The frame pulse is programmable for polarity and width.
7.1.2
Holdover Mode
In the event of a reference failure resulting in an absence of both the primary and secondary source, the DPLL automatically reverts to Holdover mode. The last valid frequency value recorded before failure can be maintained within the Stratum 3 limits of 0.05 ppm. The hold value is wholly dependent on the drift and temperature performance of the system clock. For example, a 32 ppm oscillator may have a temperature coefficient of 0.1 ppm/C. Thus a 10C ambient change since the DPLL was last in the Locking mode will change the holdover frequency by an additional 1 ppm, which is much greater than the 0.05 ppm Stratum 3 specification. If the strict target of Stratum 3 is not required, a less restrictive oscillator can be used for the system clock. Holdover mode is typically used for a short period of time until network synchronisation is re-established.
7.1.3
Freerun Mode
In freerun mode the DPLL is programmed with a centre frequency, and can output that frequency within the Stratum 3 limits of 4.6 ppm. To achieve this the 100 MHz system clock must have an absolute frequency accuracy of 4.6 ppm. The centre frequency is programmed as a fraction of the system clock frequency.
7.1.4
Powerdown Mode
It is possible to "power down" the DPLL when it is not in use. For example, an unstructured TDM system, or use of an external DPLL would mean the internal DPLL could be switched off, saving power. The internal registers can still be accessed while the DPLL is powered down.
7.2
Reference Monitor Circuit
There are two identical reference monitor circuits, one for the primary and one for the secondary source. Each circuit will continually monitor its reference, and report the references validity. The validity criteria depends on the frequency programmed for the reference. A reference must meet all the following criteria to maintain validity: * The "period in specified range" check is performed regardless of the programmed frequency. Each period must be within a range, which is programmable for the application. Refer to the ZL50118/19/20 programmers model for details. If the programmed frequency is 1.544 MHz or 2.048 MHz, the "n periods in specified range" check will be performed. The time taken for n cycles must be within a programmed range, typically with n at 64, the time taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency.
*
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Data Sheet
The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the event of an invalid signal regardless of mode.
7.3
Locking Mode Reference Switching
When the reference source the DPLL is currently locking to becomes invalid, the DPLL's response depends on which one of the failure detect modes has been chosen: autodetect, forced primary, or forced secondary. One of these failure detect modes must be chosen via the FDM1:0 bits of the DOM register. After a device reset via the SYSTEM_RESET pin, the autodetect mode is selected. In autodetect mode (automatic reference switching) if both references are valid the DPLL will synchronise to the preferred reference. If the preferred reference becomes unreliable, the DPLL continues driving its output clock in a stable holdover state until it makes a switch to the backup reference. If the preferred reference recovers, the DPLL makes a switch back to the preferred reference. If necessary, the switch back can be prevented by changing the preferred reference using the REFSEL bit in the DOM register, after the switch to the backup reference has occurred. If both references are unreliable, the DPLL will drive its output clock using the stable holdover values until one of the references becomes valid. In forced primary mode, the DPLL will synchronise to the primary reference only. The DPLL will not switch to the secondary reference under any circumstances including the loss of the primary reference. In this condition, the DPLL remains in holdover mode until the primary reference recovers. Similarly in forced secondary mode, the DPLL will synchronise to the secondary reference only, and will not switch to the primary reference. Again, a failure of the secondary reference will cause the DPLL to enter holdover mode, until such time as the secondary reference recovers. The choice of preferred reference has no effect in these modes. When a conventional PLL is locked to its reference, there is no phase difference between the input reference and the PLL output. For the DPLL, the input references can have any phase relationship between them. During a reference switch, if the DPLL output follows the phase of the new reference, a large phase jump could occur. The phase jump would be transferred to the TDM outputs. The DPLL's MTIE (Maximum Time Interval Error) feature preserves the continuity of the DPLL output so that it appears no reference switch had occurred. The MTIE circuit is not perfect however, and a small Time Interval Error is still incurred per reference switch. To align the DPLL output clock to the nearest edge of the selected input reference, the MTIE reset bit (MRST bit in the DOM register) can be used. Unlike some designs, switching between references which are at different nominal frequencies do not require intervention such as a system reset.
7.4
Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to maintain the synchronization. The locking range is programmable up to 372 ppm. Note that the locking range relates to the system clock frequency. If the external oscillator has a tolerance of -100 ppm, and the locking range is programmed to 200 ppm, the actual locking range is the programmed value shifted by the system clock tolerance to become -300 ppm to +100 ppm.
7.5
Locking Time
The Locking Time is the time it takes the synchroniser to phase lock to the input signal. Phase lock occurs when the input and output signals are not changing in phase with respect to each other (not including jitter).
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Locking time is very difficult to determine because it is affected by many factors including: * * * * initial input to output phase difference initial input to output frequency difference DPLL Loop Filter DPLL Limiter (phase slope)
Data Sheet
Although a short phase lock time is desirable, it is not always achievable due to other synchroniser requirements. For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking time; and a better (smaller) phase slope performance will increase locking time. Additionally, the locking time is dependent on the p_shift value. The DPLL Loop Filter and Limiter have been optimised to meet the Telcordia GR-1244-CORE jitter transfer and phase alignment speed requirements. The phase lock time is guaranteed to be no greater than 30 seconds when using the recommended Stratum 3 and Stratum 4/4E register settings.
7.6
Lock Status
The DPLL has a Lock Status Indicator and a corresponding Lock Change Interrupt. The response of the Lock Status Indicator is a function of the programmed Lock Detect Interval (LDI) and Lock Detect Threshold (LDT) values in the dpll_ldetect register. The LDT register can be programmed to set the jitter tolerance level of the Lock Status Indicator. To determine if the DPLL has achieved lock the Lock Status Indicator must be high for a period of at least 30 seconds. When the DPLL loses lock the Lock Status Indicator will go low after LDI x 125 s.
7.7
Jitter
The DPLL is designed to withstand, and improve inherent jitter in the TDM clock domain.
7.7.1
Acceptance of Input Wander
For T1(1.544 MHz), E1(2.048 MHz) and J2(6.312 MHz) input frequencies, the DPLL will accept a wander of up to 1023UIpp at 0.1 Hz to conform with the relevant specifications. For the 8 kHz (frame rate) and 64 kHz (the divided down output for T3/E3) input frequencies, the wander acceptance is limited to 1 UI (0.1 Hz). This principle is illustrated in Table 24.
7.7.2
Intrinsic Jitter
Intrinsic jitter is the jitter produced by a synchronizer and measured at its output. It is measured by applying a jitter free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non synchronizing mode such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable standards. The intrinsic jitter in the DPLL is reduced to less than 1 ns p-p1 by an internal Tapped Delay Line (TDL). The DPLL can be programmed so that the output clock meets all the Stratum 3 requirements of Telcordia GR-1244-CORE. Stratum 4/4E is also supported.
1. There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter up to 1 master clock period is possible, i.e. 10 ns p-p. b) In holdover mode, if a huge amount of jitter had been present prior to entering holdover, then an additional 2 ns p-p is possible.
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7.7.3 Jitter Tolerance
Data Sheet
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards. The DPLL's jitter tolerance can be programmed to meet Telcordia GR-1244-CORE DS1 reference input jitter tolerance requirements.
7.7.4
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than larger ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g. 75% of the specified maximum jitter tolerance). The internal DPLL is a first order type 2 component, so a frequency offset doesn't result in a phase offset. Stratum 3 requires a -3 dB frequency of less than 3 Hz. The nature of the filter results in some peaking, resulting in a -3dB frequency of 1.9 Hz and a 0.08 dB peak with a system clock frequency of 100 MHz assuming a p_shift value of 2. The transfer function is illustrated in Figure 19 and in more detail in Figure 20. Increasing the p_shift value increases the speed the DPLL will lock to the required frequency and reduces the peak, but also reduces the tolerance to jitter - so the p_shift value must be programmed correctly to meet Stratum 3 or Stratum 4/4E jitter transfer characteristics. This is done automatically in the API.
7.8
Maximum Time Interval Error (MTIE)
In order to meet several standards requirements, the phase shift of the DPLL output must be controlled. A potential phase shift occurs every time the DPLL is re-arranged by changing reference source signal, or the mode. In order to meet the requirements of Stratum 3, the DPLL will shift phase by no more than 20 ns per re-arrangement. Additionally the speed at which the change occurs is also critical. A large step change in output frequency is undesirable. The rate of change is programmable using the skew register, up to a maximum of 15.4 ns / 125 s (124 ppm).
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Data Sheet
Figure 19 - Jitter Transfer Function
Figure 20 - Jitter Transfer Function - Detail
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8.0 Memory Map and Register definitions
Data Sheet
All memory map and register definitions are included in the ZL50118/19/20 Programmers Model document.
9.0
DC Characteristics
Absolute Maximum Ratings*
Parameter I/O Supply Voltage Core Supply Voltage PLL Supply Voltage Input Voltage Input Voltage (5 V tolerant inputs) Continuous current at digital inputs Continuous current at digital outputs Package power dissipation Storage Temperature Symbol VDD_IO VDD_CORE VDD_PLL VI VI_5V IIN IO PD TS Min. -0.5 -0.5 -0.5 -0.5 -0.5 -55 Max. 5.0 2.5 2.5 VDD + 0.5 7.0 10 15 4 +125 Units V V V V V mA mA W C
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated. * The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.
Recommended Operating Conditions Characteristics Operating Temperature Junction temperature Positive Supply Voltage, I/O Positive Supply Voltage, Core Positive Supply Voltage, Core Input Voltage Low - all inputs Input Voltage High Input Voltage High, 5 V tolerant inputs Symbol TOP TJ VDD_IO VDD_CORE VDD_PLL VIL VIH VIH_5V Min. -40 -40 3.0 1.65 1.65 2.0 2.0 Typ. 25 3.3 1.8 1.8 Max. +85 125 3.6 1.95 1.95 0.8 VDD_IO 5.5 Units C C V V V V V V Test Condition
Typical figures are at 25C and are for design aid only, they are not guaranteed and not subject to production testing. Voltage measurements are with respect to ground (VSS) unless otherwise stated.
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Data Sheet
DC Electrical Characteristics - Typical characteristics are at 1.8 V core, 3.3 V I/O, 25C and typical processing. The min. and max. values are defined over all process conditions, from -40 to 125C junction temperature, core voltage 1.65 to 1.95 V and I/O voltage 3.0 and 3.6 V unless otherwise stated. Characteristics Input Leakage Output (High impedance) Leakage Input Capacitance Output Capacitance Pullup Current Pullup Current, 5 V tolerant inputs Pullup Current Pullup Current, 5 V tolerant inputs Core 1.8 V supply current PLL 1.8 V supply current I/O 3.3 V supply current
Note 1: Note 2:
Symbol ILEIP ILEOP CIP COP IPU IPU_5V IPU IPU_5V IDD_CORE IDD_PLL IDD_IO
Min.
Typ.
Max. 1 1
Units. A A pF pF A A A A
Test Condition No pull up/down VDD_IO = 3.6 V No pull up/down VDD_IO = 3.6 V
1 4 -27 -110 27 110 950 1.30 120
Input at 0 V Input at 0 V Input at VDD_IO Input at VDD_IO Note 1,2
mA mA mA
Note 1,2
The IO and Core supply current worst case figures apply to different scenarios and can not simply be summed for a total figure. For a clearer indication of power consumption, please refer to Section 11.0. Worst case assumes the maximum number of active contexts and channels. Figures are for the ZL50120. For an indication of typical power consumption, please refer to Section 11.0.
Input Levels Characteristics Input Low Voltage Input High Voltage Positive Schmitt Threshold Negative Schmitt Threshold Output Levels Characteristics Output Low Voltage Symbol VOL Min. Typ. Max. 0.4 Units V Test Condition IOL = 6 mA. IOL = 12 mA for packet interface (m*) pins and GPIO pins. IOL = 24 mA for LED pins. IOH = 6 mA. IOH = 12 mA for packet interface (m*) pins and GPIO pins. IOH = 24 mA for LED pins. Symbol VIL VIH VT+ VT2.0 1.6 1.2 Min. Typ. Max. 0.8 Units V V V V Test Condition
Output High Voltage
VOH
2.4
V
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10.0
10.1
Data Sheet
AC Characteristics
TDM Interface Timing - ST-BUS
The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device sourcing the data, or Master mode, where the TDM clocks are generated from the ZL50118/19/20.
10.1.1
ST-BUS Slave Clock Mode
TDM ST-BUS Slave Timing Specification Data Format ST-BUS 8.192 Mbps mode ST-BUS 2.048 Mbps mode All Modes Parameter TDM_CLKi Period TDM_CLKi High TDM_CLKi Low TDM_CLKi Period TDM_CLKi High TDM_CLKi Low TDM_F0i Width 8.192 Mbps 2.048 Mbps TDM_F0i Setup Time Symbol tC16IP tC16IH tC16IL tC4IP tC4IH tC4IL tFOIW 50 200 tFOIS 5 300 ns With respect to TDM_CLKi falling edge With respect to TDM_CLKi falling edge With respect to TDM_CLKi Load CL = 50 pF With respect to TDM_CLKi With respect to TDM_CLKi Min. 54 27 27 110 110 Typ. 60 244.1 Max. 66 33 33 134 134 Units ns ns ns ns ns ns ns Notes
TDM_F0i Hold Time
tFOIH
5
-
-
ns
TDM_STo Delay
tSTOD
1
-
20
ns
TDM_STi Setup Time TDM_STi Hold Time
tSTIS tSTIH
5 5
-
-
ns ns
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Data Sheet
In synchronous mode the clock must be within the locking range of the DPLL to function correctly ( 245 ppm). In asynchronous mode, the clock may be any frequency.
Channel 127 bit 1
Channel 127 bit 0
Channel 0 bit 7 tC16IP
Channel 0 bit 6
TDM_CKLI tFOIH tFOIS TDM_F0i tSTIH tSTIS TDM_STi tSTOD TDM_STo Channel 127 bit 1 Channel 127 bit 0 tSTOD Channel 0 bit 7 tSTIH tSTIS tSTIH tSTIS
Ch0 bit7
tSTOD
Figure 21 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps
Channel 31 Bit 0 TDM_CLKI (2.048 MHz) tC4IP TDM_CLKI (4.096 MHz) tFOIS TDM_F0i tFOIW
Channel 0 Bit 7 tC2IP
Channel 0 Bit 6
tFOIH
tSTIH tSTIS TDM_STi tSTOD TDM_STo Ch 31 Bit 0 Ch 0 Bit 7 tSTOD Ch 0 Bit 6
Figure 22 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps
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10.1.2 ST-BUS Master Clock Mode
Parameter TDM_CLKo Period TDM_CLKo High TDM_CLKo Low ST-BUS 2.048 Mbps mode All Modes TDM_CLKo Period TDM_CLKo High TDM_CLKo Low TDM_F0o Delay Symbol tC16OP tC16OH tC16OL tC4OP tC4OH tC4OL tFOD Min. 54.0 23.0 23.0 237.0 115.0 115.0 Typ. 61.0 244.1 Max. 68.0 37.0 37.0 251.0 129.0 129.0 25 Units ns ns ns ns ns ns ns
Data Sheet
Data Format ST-BUS 8.192 Mbps mode
Notes
With respect to TDM_CLKo falling edge With respect to TDM_CLKo falling edge With respect to TDM_CLKo falling edge With respect to TDM_CLKo With respect to TDM_CLKo
TDM_STo Delay Active-Active TDM_STo Delay Active to HiZ and HiZ to Active TDM_STi Setup Time TDM_STi Hold Time
tSTOD
-
-
5
ns
tDZ, tZD
-
-
33
ns
tSTIS tSTIH
5 5
-
-
ns ns
Table 25 - TDM ST-BUS Master Timing Specification
Channel 127 Bit 0 tC16OP TDM_CLKO tFOD TDM_F0o tSTIH tSTIS TDM_STi B0
Channel 0 Bit 7
Channel 0 Bit 6
tFOD tSTIH tSTIS B7 tSTOD tSTOD Ch 0 Bit 7 Ch 0 Bit 6 B6
TDM_STo
Ch 127 Bit 0
Figure 23 - TDM Bus Master Mode Timing at 8.192 Mbps
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Data Sheet
Channel 31 Bit 0
Channel 0 Bit 7 tC2OP
Channel 0 Bit 6
TDM_CLKO (2.048 MHz) tC4OP TDM_CLKO (4.096 MHz) tFOD TDM_F0o tSTIH tSTIS TDM_STi tSTOD TDM_STo Ch 31 Bit 0 Ch 0 Bit 7 tSTOD Ch 0 Bit 6 tFOD
Figure 24 - TDM Bus Master Mode Timing at 2.048 Mbps
10.2
TDM Interface Timing - H.110 Mode
These parameters are based on the H.110 Specification from the Enterprise Computer Telephony Forum (ECTF) 1997. Parameter TDM_C8 Period TDM_C8 High TDM_C8 Low TDM_D Output Delay TDM_D Output to HiZ TDM_D HiZ to Output TDM_D Input Delay to Valid TDM_D Input Delay to Invalid TDM_FRAME width TDM_FRAME setup TDM_FRAME hold Phase Correction
Note Note Note Note Note 1: 2: 3: 4: 5:
Symbol tC8P tC8H tC8L tDOD tDOZ tZDO tDV tDIV tFP tFS tFH F
Min. 122.066- 63- 63- 0 0 0 102 90 45 45 0
Typ. 122 122 -
Max. 122.074+ 69+ 69+ 11 33 11 83 112 180 90 90 10
Units ns ns ns ns ns ns ns ns ns ns ns ns
Notes Note 1 Note 2
Load - 12 pF Load - 12 pF Note 3 Load - 12 pF Note 3 Note 4 Note 4 Note 5
Note 6
Table 26 - TDM H.110 Timing Specification
TDM_C8 and TDM_FRAME signals are required to meet the same timing standards and so are not defined independently. TDM_C8 corresponds to pin TDM_CLKi. tDOZ and t ZDO apply at every time-slot boundary. Refer to H.110 Standard from Enterprise Computer Telephony Forum (ECTF) for the source of these numbers. The TDM_FRAME signal is centred on the rising edge of TDM_C8. All timing measurements are based on this rising edge point; TDM_FRAME corresponds to pin TDM_F0i. Phase correction () results from DPLL timing corrections.
Note 6:
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Data Sheet
Ts 127 Bit 8 tC8H TDM_C8 tFS TDM_FRAME
Ts 0 Bit 1 tC8P tC8L
Ts 0 Bit 2
tFP
tFH
tDIV tDV TDM_D Input tZDO tDOZ TDM_D Output Ts 127 Bit 8 Ts 0 Bit 1 tDOD Ts 0 Bit 2
Figure 25 - H.110 Timing Diagram
10.3
TDM Interface Timing - H-MVIP
These parameters are based on the Multi-Vendor Integration Protocol (MVIP) specification for an H-MVIP Bus, Release 1.1a (1997). Positive transitions of TDM_C2 are synchronous with the falling edges of TDM_C4 and TDM_C16. The signals TDM_C2, TDM_C4 and TDM_C16 correspond with pins TDM_CLKi. The signals TDM_F0 correspond with pins TDM_F0i. The signals TDM_HDS correspond with pins TDM_STi and TDM_STo. Parameter TDM_C2 Period TDM_C2 High TDM_C2 Low TDM_C4 Period TDM_C4 High TDM_C4 Low TDM_C16 Period TDM_C16 High TDM_C16 Low TDM_HDS Output Delay TDM_HDS Output Delay TDM_HDS Output to HiZ TDM_HDS Input Setup TDM_HDS Input Hold TDM_F0 width Symbol tC2P tC2H tC2L tC4P tC4H tC4L tC16P tC16H tC16L tPD tPD tHZD tS tH tFW Min. 487.8 220 220 243.9 110 110 60.9 30 30 30 30 200 Typ. 488.3 244.1 61.0 244 Max. 488.8 268 268 244.4 134 134 61.1 31 31 30 100 30 0 0 300 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns At 8.192 Mbps At 2.048 Mbps Notes
Table 27 - TDM H-MVIP Timing Specification
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Parameter TDM_F0 setup TDM_F0 hold Symbol tFS tFH Min. 50 50 Typ. Max. 150 150 Units ns ns
Data Sheet
Notes
Table 27 - TDM H-MVIP Timing Specification (continued)
Ts 127 Bit 7 tC16P tC16L TDM_C16 tFS TDM_F0 tFW tFH
Ts 0 Bit 0 tC16H
Ts 0 Bit 1
tS TDM_HDS Input tHZD TDM_HDS Output Ch 127 Bit 7 tPD Ch 0 Bit 0
tH
Figure 26 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps)
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10.4 TDM LIU Interface Timing
Data Sheet
The TDM Interface can be used to directly drive into a Line Interface Unit (LIU). The interface can work in this mode with E1, DS1, J2, E3 and DS3. The frame pulse is not present, just data and clock is transmitted and received. Table 28 shows timing for DS3, which would be the most stringent requirement. Parameter TDM_TXCLK Period TDM_TXCLK High TDM_TXCLK Low TDM_RXCLK Period TDM_RXCLK High TDM_RXCLK Low TDM_TXDATA Output Delay TDM_RXDATA Input Setup TDM_RXDATA Input Hold Symbol tCTP tCTH tCTL tCRP tCRH tCRL tPD tS tH 9.0 9.0 3 6 3 10 6.7 6.7 22.353 Min. Typ. 22.353 Max. Units ns ns ns ns ns ns ns ns ns DS3 clock Notes DS3 clock
Table 28 - TDM - LIU Structured Transmission/Reception
tCTP TDM_TXCLK
tCTH
tCTL
tPD TDM_TXDATA tCRP TDM_RXCLK tS TDM_RXDATA tH tCRH tCRL
Figure 27 - TDM-LIU Structured Transmission/Reception
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10.5 PAC Interface Timing
Parameter TDM_CLKiP High / Low Pulsewidth TDM_CLKiS High / Low Pulsewidth Symbol tCPP tCSP Min. 10 10 Typ. Max. Units ns ns
Data Sheet
Notes
Table 29 - PAC Timing Specification
10.6
Packet Interface Timing
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
10.6.1
MII Transmit Timing
100 Mbps Min. 14 14 1 1 1 Typ. 40 Max. 26 26 5 5 25 25 25
Parameter TXCLK period TXCLK high time TXCLK low time TXCLK rise time TXCLK fall time TXCLK rise to TXD[3:0] active delay (TXCLK rising edge) TXCLK to TXEN active delay (TXCLK rising edge) TXCLK to TXER active delay (TXCLK rising edge)
Symbol tCC tCHI tCLO tCR tCF tDV tEV tER
Units ns ns ns ns ns ns ns ns
Notes
Load = 25 pF Load = 25 pF Load = 25 pF
Table 30 - MII Transmit Timing - 100 Mbps
tCC TXCLK tEV TXEN tDV TXD[3:0] tER TXER tER
tCL
tCH
tEV
Figure 28 - MII Transmit Timing Diagram
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10.6.2 MII Receive Timing
100 Mbps Min. 14 14 10 5 10 5 10 5 Typ. 40 20 20 Max. 26 26 5 5 -
Data Sheet
Parameter RXCLK period RXCLK high wide time RXCLK low wide time RXCLK rise time RXCLK fall time RXD[3:0] setup time (RXCLK rising edge) RXD[3:0] hold time (RXCLK rising edge) RXDV input setup time (RXCLK rising edge) RXDV input hold time (RXCLK rising edge) RXER input setup time (RXCL edge) RXER input hold time (RXCLK rising edge)
Symbol tCC tCH tCL tCR tCF tDS tDH tDVS tDVH tERS tERH
Units ns ns ns ns ns ns ns ns ns ns ns
Notes
Table 31 - MII Receive Timing - 100 Mbps
tCC RXCLK tDVS RXDV tDH tDS RXD[3:0] tERH tERS RXER
tCLO
tCHI
tDVH
Figure 29 - MII Receive Timing Diagram
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10.6.3 GMII Transmit Timing
Data Sheet
Parameter GTXCLK period GTXCLK high time GTXCLK low time GTXCLK rise time GTXCLK fall time GTXCLK rise to TXD[7:0] active delay GTXCLK rise to TXEN active delay GTXCLK rise to TXER active delay
Symbol tGC tGCH tGCL tGCR tGCF tDV tEV tER
1000 Mbps Min. 7.5 2.5 2.5 1.5 2 1 Typ. Max. 8.5 1 1 6 6 6
Units ns ns ns ns ns ns ns ns
Notes
Load = 25 pF Load = 25 pF Load = 25 pF
Table 32 - GMII Transmit Timing - 1000 Mbps
tCC GTXCLK tEV TXEN tDV TXD[3:0] tER TXER tER
tCL
tCH
tEV
Figure 30 - GMII Transmit Timing Diagram
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10.6.4 GMII Receive Timing
1000 Mbps Min. 7.5 2.5 2.5 2 1 2 1 2 1 Typ. Max. 8.5 1 1 -
Data Sheet
Parameter RXCLK period RXCLK high wide time RXCLK low wide time RXCLK rise time RXCLK fall time RXD[7:0] setup time (RXCLK rising edge) RXD[7:0] hold time (RXCLK rising edge) RXDV setup time (RXCLK rising edge) RXDV hold time (RXCLK rising edge) RXER setup time (RXCLK rising edge) RXER hold time (RXCLK rising edge)
Symbol tCC tCH tCL tCR tCF tDS tDH tDVS tDVH tERS tERH
Units ns ns ns ns ns ns ns ns ns ns ns
Notes
Table 33 - GMII Receive Timing - 1000 Mbps
tCC RXCLK tDVS RXDV tDH tDS RXD[7:0] tERH tERS RXER
tCLO
tCHI
tDVH
Figure 31 - GMII Receive Timing Diagram
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10.6.5 TBI Interface Timing
1000 Mbps Min. 7.5 2.5 2.5 1 15 5 5 2 1 7.5 2.5 2.5 Typ. 16 Max. 8.5 6 17 2 2 8.5 ns ns ns ns ns ns ns ns ns ns
Data Sheet
Parameter GTXCLK period GTXCLK high wide time GTXCLK low wide time TXD[9:0] Output Delay (GTXCLK rising edge) RCB0/RBC1 period RCB0/RBC1 high wide time RCB0/RBC1 low wide time RCB0/RBC1 rise time RCB0/RBC1 fall time RXD[9:0] setup time (RCB0 rising edge) RXD[9:0] hold time (RCB0 rising edge) REFCLK period REFCLK high wide time REFCLK low wide time
Symbol tGC tGH tGL tDV tRC tRH tRL tRR tRF tDS tDH tFC tFH tFL
Units ns ns ns
Notes
Load = 25 pF
Table 34 - TBI Timing - 1000 Mbps
tGC
GTXCLK
TXD[9:0] Signal_Detect
/I/
tDV /S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/
/I/
Figure 32 - TBI Transmit Timing Diagram
tRC RBC1 tRC RBC0 tDS /D/ /D/ tDH /D/ /D/ /D/ tDS /D/ /D/ /D/ tDH /D/ /T/ /R/ /I/
RXD[9:0] Signal_Detect
/I/
/S/ /D/
/D/
/D/
Figure 33 - TBI Receive Timing Diagram
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10.6.6 Management Interface Timing
Data Sheet
The management interface is common for all inputs and consists of a serial data I/O line and a clock line. Parameter M_MDC Clock Output period M_MDC high M_MDC low M_MDC rise time M_MDC fall time M_MDIO setup time (MDC rising edge) M_MDIO hold time (M_MDC rising edge) M_MDIO Output Delay (M_MDC rising edge)
Note 1: Note 2:
Symbol tMP tMHI tMLO tMR tMF tMS tMH tMD
Min. 1990 900 900 10 10 1
Typ. 2000 1000 1000 -
Max. 2010 1100 1100 5 5 300
Units ns ns ns ns ns ns ns ns
Notes Note 1
Note 1 Note 1 Note 2
Table 35 - MAC Management Timing Specification
Refer to Clause 22 in IEEE802.3 (2000) Standard for input/output signal timing characteristics. Refer to Clause 22C.4 in IEEE802.3 (2000) Standard for output load description of MDIO.
tMHI M_MDC tMS M_MDIO tMH
tMLO
Figure 34 - Management Interface Timing for Ethernet Port - Read
tMP M_MDC tMD M_MDIO
Figure 35 - Management Interface Timing for Ethernet Port - Write
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10.7 CPU Interface Timing
Parameter CPU_CLK Period CPU_CLK High Time CPU_CLK Low Time CPU_CLK Rise Time CPU_CLK Fall Time CPU_ADDR[23:2] Setup Time CPU_ADDR[23:2] Hold Time CPU_DATA[31:0] Setup Time CPU_DATA[31:0] Hold Time CPU_CS Setup Time CPU_CS Hold Time CPU_WE/CPU_OE Setup Time CPU_WE/CPU_OE Hold Time CPU_TS_ALE Setup Time CPU_TS_ALE Hold Time CPU_SDACK1/CPU_SDACK2 Setup Time CPU_SDACK1/CPU_SDACK2 Hold Time CPU_TA Output Valid Delay CPU_DREQ0/CPU_DREQ1 Output Valid Delay CPU_IREQ0/CPU_IREQ1 Output Valid Delay CPU_DATA[31:0] Output Valid Delay CPU_CS to Output Data Valid CPU_OE to Output Data Valid CPU_CLK(falling) to CPU_TA Valid
Note 1: Note 2:
Data Sheet
Symbol tCC tCCH tCCL tCCR tCCF tCAS tCAH tCDS tCDH tCSS tCSH tCES tCEH tCTS tCTH tCKS tCKH tCTV tCWV tCRV tCDV tSDV tODV tOTV
Min.
Typ. 15.152
Max.
Units ns ns ns
Notes
6 6 4 4 4 2 4 2 4 2 5 2 4 2 2 2 2 2 2 2 3.2 3.3 3.2 11.3 6 6 7 10.4 10.4 9.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1, 2 Note 1 Note 1 Note 1
Table 36 - CPU Timing Specification
Load = 50 pF maximum The maximum value of t CTV may cause setup violations if directly connected to the MPC8260. See Section 12.2 for details of how to accommodate this during board design.
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Data Sheet
The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
tCC CPU_CLK tCAS CPU_ADDR[23:2] tCSS CPU_CS tCES CPU_OE CPU_WE tCTS CPU_TS_ALE tSDV CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tODV tCDV tCTH tCAH
0 or more cycles
tCSH tCEH
tODV tSDV tOTV
NOTE: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output.
Figure 36 - CPU Read - MPC8260
tCC 0 or more cycles CPU_CLK tCAS CPU_ADDR[23:2] tCSS CPU_CS CPU_OE tCES CPU_WE tCTH tCTS CPU_TS_ALE tCDS CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tCDH tCEH tCAH
0 or more cycles
tCSH
tOTV
NOTE: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
Figure 37 - CPU Write - MPC8260
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tCC CPU_CLK tCWV CPU_DREQ1 tCKS CPU_SDACK2 tCSS CPU_CS tCES CPU_OE CPU_WE tCTH tCTS CPU_TS_ALE tSDV CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tODV tCDV tODV tSDV tCEH tCSH tCKH tCWV
Data Sheet
0 or more cycles
tOTV
NOTE: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable
the CPU_DATA output.
Figure 38 - CPU DMA Read - MPC8260
tCC CPU_CLK tCWV CPU_DREQ0 tCKS CPU_SDACK1 tCSS CPU_CS CPU_OE tCES CPU_WE tCTS CPU_TS_ALE tCDS CPU_DATA[31:0] tOTV CPU_TA NOTE: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time. Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed. tCTV tCTV tCDH tCTH tCEH tCKH tCWV
0 or more cycles
tCSH
tOTV
Figure 39 - CPU DMA Write - MPC8260
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10.8 System Function Port
Parameter SYSTEM_CLK Frequency SYSTEM_CLK accuracy (synchronous master mode) SYSTEM_CLK accuracy (synchronous slave mode and asynchronous mode)
Note 1:
Data Sheet
Symbol CLKFR CLKACS CLKACA
Min. -
Typ. 100 -
Max. 30 200
Units MHz ppm ppm
Notes Note 1 and Note 2 Note 3 Note 4
Table 37 - System Clock Timing
The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature coefficient of 0.1 ppm/C, a 10C change in temperature while the DPLL is in will result in a frequency accuracy offset of 1 ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift. The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e., frequency of clock output equals 8.192 MHz SYSTEM_CLK accuracy 0.005 ppm). The absolute SYSTEM_CLK accuracy must be controlled to 30 ppm in synchronous master mode to enable the internal DPLL to function correctly. In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may be relaxed slightly.
Note 2:
Note 3: Note 4:
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10.9 JTAG Interface Timing
Parameter JTAG_CLK period JTAG_CLK clock pulse width JTAG_CLK rise and fall time JTAG_TRST setup time Symbol tJCP tLOW, tHIGH tJRF tRSTSU Min. 40 20 0 10 Typ. 100 3 Max. Units ns ns ns ns
Data Sheet
Notes
With respect to JTAG_CLK falling edge. Note 1 Note 2 Note 2 Note 3 Note 3
JTAG_TRST assert time Input data setup time Input Data hold time JTAG_CLK to Output data valid JTAG_CLK to Output data high impedance JTAG_TMS, JTAG_TDI setup time JTAG_TMS, JTAG_TDI hold time JTAG_TDO delay JTAG_TDO delay to high impedance
Note 1: Note 2: Note 3:
tRST tJSU tJH tJDV tJZ tTPSU tTPH tTOPDV tTPZ
10 5 15 0 0 5 15 0 0
-
20 20 15 15
ns ns ns ns ns ns ns ns ns
Table 38 - JTAG Interface Timing
JTAG_TRST is an asynchronous signal. The setup time is for test purposes only. Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK. Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK.
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Data Sheet
tHIGH JTAG_TCK tTPH
tLOW
tJCP
tTPSU JTAG_TMS
tTPSU JTAG_TDI Don't Care tTOPDV JTAG_TDO HiZ
tTPH DC tTPZ HiZ
Figure 40 - JTAG Signal Timing
tLOW
JTAG_TCK
tHIGH
tRST
JTAG_TRST
tRSTSU
Figure 41 - JTAG Clock and Reset Timing
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11.0 Power Characteristics
Data Sheet
The following graph in Figure 42 illustrates typical power consumption figures for the ZL50118/19/20 family. Typical characteristics are at 1.8 V core, 3.3V I/O, 25C and typical processing.
ZL50118/19/20 Power Consumption (Typical Conditions)
1.410 1.400 Power (W) 1.390 1.380 1.370 1.360 1.350 1 2 3 4 Number of Active E1 Unstructured Contexts
Figure 42 - ZL50118/19/20 Power Consumption Plot
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12.0 Design and Layout Guidelines
Data Sheet
This guide will provide information and guidance for PCB layouts when using the ZL50118/19/20. Specific areas of guidance are: * * High Speed Clock and Data, Outputs and Inputs CPU_TA Output
12.1
High Speed Clock & Data Interfaces
On the ZL50118/19/20 series of devices there are four high-speed data interfaces that need consideration when laying out a PCB to ensure correct termination of traces and the reduction of crosstalk noise. The interfaces being: * * * GMAC Interfaces TDM Interface CPU Interface
It is recommended that the outputs are suitably terminated using a series termination through a resistor as close to the output pin as possible. The purpose of the series termination resistor is to reduce reflections on the line. The value of the series termination and the length of trace the output can drive will depend on the driver output impedance, the characteristic impedance of the PCB trace (recommend 50 ohm), the distributed trace capacitance and the load capacitance. As a general rule of thumb, if the trace length is less than 1/6th of the equivalent length of the rise and fall times, then a series termination may not be required. the equivalent length of rise time = rise time (ps) / delay (ps/mm) For example: Typical FR4 board delay = 6.8 ps/mm Typical rise/fall time for a ZL50118/19/20 output = 2.5 ns critical track length = (1/6) x (2500/6.8) = 61 mm Therefore tracks longer than 61 mm will require termination. As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace and therefore it should be minimized in the layout. The voltage that the external fields cause is proportional to the strength of the field and the length of the trace exposed to the field. Therefore to minimize the effect of crosstalk some basic guidelines should be followed. First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or by placing guard traces between the signals usually held ground potential. Particular effort should be made to minimize crosstalk from ZL50118/19/20 outputs and ensuring fast rise time to these inputs.
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In Summary: * * * * Place series termination resistors as close to the pins as possible minimize output capacitance Keep common interface traces close to the same length to avoid skew Protect input clocks and signals from crosstalk
Data Sheet
12.1.1
GMAC Interface - Special Considerations During Layout
The GMII interface passes data to and from the ZL50118/19/20 with their related transmit and receive clocks. It is therefore recommended that the trace lengths for transmit related signals and their clock and the receive related signals and their clock are kept to the same length. By doing this the skew between individual signals and their related clock will be minimized.
12.1.2
TDM Interface - Special Considerations During Layout
Although the data rate of this interface is low the outputs edge speeds share the characteristics of the higher data rate outputs and therefore must be treated with the same care extended to the other interfaces with particular reference to the lower stream numbers which support the higher data rates. The TDM interface has numerous clocking schemes and as a result of this the input clock traces to the ZL50118/19/20 devices should be treated with care.
12.1.3
Summary
Particular effort should be made to minimize crosstalk from ZL50118/19/20 outputs and ensuring fast rise time to these inputs. In Summary: * * * * Place series termination resistors as close to the pins as possible minimize output capacitance Keep common interface traces close to the same length to avoid skew Protect input clocks and signals from crosstalk
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12.2 CPU TA Output
Data Sheet
The CPU_TA output signal from the ZL50118/19/20 is a critical handshake signal to the CPU that ensures the correct completion of a bus transaction between the two devices. As the signal is critical, it is recommend that the circuit shown in Figure 43 is implemented in systems operating above 40 MHz bus frequency to ensure robust operation under all conditions. The following external logic is required to implement the circuit: * * * * 74LCX74 dual D-type flip-flop (one section of two) 74LCX08 quad AND gate (one section of four) 74LCX125 quad tri-state buffer (one section of four) 4K7 resistor x2
+3V3
+3V3
R1 4K7
R2 4K7
CPU_TA from ZL50118/19/20
CPU_TA to CPU
D
Q
CPU_CLK to ZL50118/19/20
CPU_CS to ZL50118/19/20
Figure 43 - CPU_TA Board Circuit The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be fitted to ensure correct operation of the TA input to the processor. It is recommended that the logic is fitted close to the ZL50118/19/20 and that the clock to the 74LCX74 is derived from the same clock source as that input to the ZL50118/19/20.
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13.0
13.1
* * * * * * * * * * * * * * * * * * * * * * *
Data Sheet
Reference Documents
External Standards/Specifications
IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer ECTF H.110 Revision 1.0; Hardware Compatibility Specification H-MVIP (GO-MVIP) Standard Release 1.1a; Multi-Vendor Integration Protocol MPC8260AEC/D Revision 0.7; Motorola MPC8260 Family Hardware Specification RFC 768; UDP RFC 791; IPv4 RFC2460; IPv6 RFC 1889; RTP RFC 2661; L2TP RFC 1213; MIB II RFC 1757; Remote Network Monitoring MIB (for SMIv1) RFC 2819; Remote Network Monitoring MIB (for SMIv2) RFC 2863; Interfaces Group MIB CCITT G.712; TDM Timing Specification (Method 2) G.823; Control of Jitter/Wander with digital networks based on the 2.048 Mbps hierarchy G.824; Control of Jitter/Wander with digital networks based on the 1.544 Mbps hierarchy ANSI T1.101 Stratum 3/4 Telcordia GR-1244-CORE Stratum 3/4/4e IETF PWE3 draft-ietf-l2tpext-l2tp-base-02 IETF PWE3 draft-ietf-pwe3-cesopsn IETF PWE3 draft-ietf-pwe3-satop ITU-T Y.1413 TDM-MPLS Network Interworking
13.2
*
Zarlink Standards
MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification
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14.0
API ATM CDP CES
Data Sheet
Glossary
Application Program Interface Asynchronous Transfer Mode Context Descriptor Protocol (the protocol used by Zarlink's MT9088x family of TDM-Packet devices) Circuit Emulation Services
CESoPSN Circuit Emulation Services over Packet Switched Networks CONTEXTA programmed connection of a number of TDM timeslots assembled into a unique packet stream. CPU DMA Central Processing Unit Direct Memory Access
DPLL Digital Phase Locked Loop DSP GMII Digital Signal Processor Gigabit Media Independent Interface
H.100/H.110High capacity TDM backplane standards H-MVIP High-performance Multi-Vendor Integration Protocol (a TDM bus standard) IETF IA IP JTAG L2TP LAN LIU MAC MEF MFA MII MIB Internet Engineering Task Force Implementation Agreement Internet Protocol (version 4, RFC 791, version 6, RFC 2460) Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level test facility) Layer 2 Tunneling Protocol (RFC 2661) Local Area Network Line Interface Unit Media Access Control Metro Ethernet Forum MPLS and Frame Relay Alliance Media Independent Interface Management Information Base
MPLS Multi Protocol Label Switching MTIE MVIP PDH PLL PRS PRX Maximum Time Interval Error Multi-Vendor Integration Protocol (a TDM bus standard) Plesiochronous Digital Hierarchy Phase Locked Loop Primary Reference Source Packet Receive
PSTN Public Switched Telephone Circuit
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PTX Packet Transmit PWE3 Pseudo-Wire Emulation Edge to Edge (a working group of the IETF) QoS RTP PE Quality of Service Real Time Protocol (RFC 1889) Protocol Engine
Data Sheet
SAToP Structure-Agnostic TDM over Packet ST BUSStandard Telecom Bus, a standard interface for TDM data streams TDL TDM UDP UI Tapped Delay Line Time Division Multiplexing User Datagram Protocol (RFC 768) Unit Interval
VLAN Virtual Local Area Network WFQ Weighted Fair Queuing
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c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1
02 June 04
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